On Tue, May 27, 2014 at 03:27:23PM +0100, Damien Lespiau wrote:
> On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > For disabling L3 clock gating we need to set bit 25 of MMIO
> > register 940c. Earlier this was being done by just writing 1
> > i
On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> For disabling L3 clock gating we need to set bit 25 of MMIO
> register 940c. Earlier this was being done by just writing 1
> into bit 25 and resetting all other bits.
> This patch modifies the routine t
On Mon, 2014-04-14 at 10:22 +, Gupta, Sourab wrote:
> On Tue, 2014-04-01 at 10:53 +0530, sourab gupta wrote:
> > On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> > > On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> > > > On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@
On Tue, 2014-04-01 at 10:53 +0530, sourab gupta wrote:
> On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> > On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> > > On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > > > From: Akash Goel
> > > >
> > > > For
On Tue, 2014-03-25 at 12:23 +0530, sourab gupta wrote:
> On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> > On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > > From: Akash Goel
> > >
> > > For disabling L3 clock gating we need to set bit 25 of MMIO
> > > regis
On Mon, 2014-03-24 at 17:56 +, Lespiau, Damien wrote:
> On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> > From: Akash Goel
> >
> > For disabling L3 clock gating we need to set bit 25 of MMIO
> > register 940c. Earlier this was being done by just writing 1
> > into bi
On Mon, Mar 24, 2014 at 11:00:07PM +0530, sourab.gu...@intel.com wrote:
> From: Akash Goel
>
> For disabling L3 clock gating we need to set bit 25 of MMIO
> register 940c. Earlier this was being done by just writing 1
> into bit 25 and resetting all other bits.
> This patch modifies the routine t
From: Akash Goel
For disabling L3 clock gating we need to set bit 25 of MMIO
register 940c. Earlier this was being done by just writing 1
into bit 25 and resetting all other bits.
This patch modifies the routine to read-modify-write of the
register, so that the values of other bits are not destro
