Re: [Intel-gfx] [PATCH v3] drm/i915/cmdparser: Limit clflush to active cachelines

On Fri, Mar 10, 2017 at 02:41:16PM +0200, Mika Kuoppala wrote: > Chris Wilson writes: > > > We only need to clflush those cachelines that we have validated to be > > read by the GPU. Userspace typically fills the batch length in > > correctly, the exceptions tend to be

Re: [Intel-gfx] [PATCH v3] drm/i915/cmdparser: Limit clflush to active cachelines

Chris Wilson writes: > We only need to clflush those cachelines that we have validated to be > read by the GPU. Userspace typically fills the batch length in > correctly, the exceptions tend to be explicit tests within igt. > > v2: Use ptr_mask_bits() to make Mika happy

[Intel-gfx] [PATCH v3] drm/i915/cmdparser: Limit clflush to active cachelines

We only need to clflush those cachelines that we have validated to be read by the GPU. Userspace typically fills the batch length in correctly, the exceptions tend to be explicit tests within igt. v2: Use ptr_mask_bits() to make Mika happy v3: cmd is not advanced on MI_BBE, so make sure to