[Intel-gfx] [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

2014-11-12 Thread ville . syrjala
From: Ville Syrjälä Currently it's possible to get visible cache dirt on scanout on LLC machines when using pwrite on the future scanout bo if its cache_level is already NONE. pwrite's "does this need clflush?" checks would decide that no clflush is necessary since the bo isn't currently pinned

Re: [Intel-gfx] [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

2014-11-12 Thread shuang . he
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang...@intel.com) -Summary- Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate BYT: pass/total=291/291->284/291 PNV: pass/total=356/356->350

Re: [Intel-gfx] [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

2014-11-14 Thread Chris Wilson
On Wed, Nov 12, 2014 at 11:47:14PM +0200, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä > > Currently it's possible to get visible cache dirt on scanout on LLC > machines when using pwrite on the future scanout bo if its cache_level > is already NONE. > > pwrite's "does this need cl

Re: [Intel-gfx] [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

2014-11-14 Thread Ville Syrjälä
On Fri, Nov 14, 2014 at 05:00:59PM +, Chris Wilson wrote: > On Wed, Nov 12, 2014 at 11:47:14PM +0200, ville.syrj...@linux.intel.com wrote: > > From: Ville Syrjälä > > > > Currently it's possible to get visible cache dirt on scanout on LLC > > machines when using pwrite on the future scanout b

Re: [Intel-gfx] [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

2014-11-15 Thread Chris Wilson
On Fri, Nov 14, 2014 at 08:35:57PM +0200, Ville Syrjälä wrote: > On Fri, Nov 14, 2014 at 05:00:59PM +, Chris Wilson wrote: > > On Wed, Nov 12, 2014 at 11:47:14PM +0200, ville.syrj...@linux.intel.com > > wrote: > > > From: Ville Syrjälä > > > > > > Currently it's possible to get visible cache