On Tue, Jul 21, 2015 at 10:45:45AM +0100, Chris Wilson wrote:
> On Tue, Jul 21, 2015 at 08:49:31AM +0200, Daniel Vetter wrote:
> > On Fri, Jul 17, 2015 at 05:10:25PM +0200, Michał Winiarski wrote:
> > > On Thu, Jul 16, 2015 at 12:37:56PM +0100, Chris Wilson wrote:
> > > > Since the hardware sometim
On Tue, Jul 21, 2015 at 08:49:31AM +0200, Daniel Vetter wrote:
> On Fri, Jul 17, 2015 at 05:10:25PM +0200, Michał Winiarski wrote:
> > On Thu, Jul 16, 2015 at 12:37:56PM +0100, Chris Wilson wrote:
> > > Since the hardware sometimes mysteriously totally flummoxes the 64bit
> > > read of a 64bit regi
On Fri, Jul 17, 2015 at 05:10:25PM +0200, Michał Winiarski wrote:
> On Thu, Jul 16, 2015 at 12:37:56PM +0100, Chris Wilson wrote:
> > Since the hardware sometimes mysteriously totally flummoxes the 64bit
> > read of a 64bit register when read using a single instruction, split the
> > read into two
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact:
shuang...@intel.com)
Task id: 6813
-Summary-
Platform Delta drm-intel-nightly Series Applied
ILK
On Thu, Jul 16, 2015 at 12:37:56PM +0100, Chris Wilson wrote:
> Since the hardware sometimes mysteriously totally flummoxes the 64bit
> read of a 64bit register when read using a single instruction, split the
> read into two instructions. Since the read here is of automatically
> incrementing times
Since the hardware sometimes mysteriously totally flummoxes the 64bit
read of a 64bit register when read using a single instruction, split the
read into two instructions. Since the read here is of automatically
incrementing timestamp counters, we also have to be very careful in
order to make sure t
