Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/guc: Make scratch register base and count flexible

2017-05-08 Thread Jani Nikula
On Mon, 08 May 2017, Joonas Lahtinen wrote: > PS. I personally don't like the enum typed bitfields, but that's an > another discussion (that's been had in the past). I'm with you on this one. It's semi-okay to define the bits as enums, but IMO a variable of an enum type should only ever be used t

Re: [Intel-gfx] [PATCH v3 2/3] drm/i915/guc: Make scratch register base and count flexible

2017-05-08 Thread Joonas Lahtinen
On pe, 2017-05-05 at 11:35 +, Michal Wajdeczko wrote: > We are using some scratch registers in MMIO based send function. > Make their base and count flexible in preparation of upcoming > GuC firmware/hardware changes. While around, change cmd len > parameter verification from WARN_ON to GEM_BUG

[Intel-gfx] [PATCH v3 2/3] drm/i915/guc: Make scratch register base and count flexible

2017-05-05 Thread Michal Wajdeczko
We are using some scratch registers in MMIO based send function. Make their base and count flexible in preparation of upcoming GuC firmware/hardware changes. While around, change cmd len parameter verification from WARN_ON to GEM_BUG_ON as we don't need this all the time. v2: call out WARN/GEM_BUG