On Tue, 2018-04-24 at 17:16 -0700, Dhinakaran Pandiyan wrote:
>
>
> On Tue, 2018-04-24 at 14:20 -0700, Rodrigo Vivi wrote:
> > On Mon, Apr 23, 2018 at 05:42:40PM -0700, Souza, Jose wrote:
> > > On Fri, 2018-04-20 at 15:57 -0700, Rodrigo Vivi wrote:
> > > > On Fri, Apr 20, 2018 at 03:27:56PM
On Tue, 2018-04-24 at 14:20 -0700, Rodrigo Vivi wrote:
> On Mon, Apr 23, 2018 at 05:42:40PM -0700, Souza, Jose wrote:
> > On Fri, 2018-04-20 at 15:57 -0700, Rodrigo Vivi wrote:
> > > On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza
> > > wrote:
> > > > Any write in any display
On Mon, Apr 23, 2018 at 05:42:40PM -0700, Souza, Jose wrote:
> On Fri, 2018-04-20 at 15:57 -0700, Rodrigo Vivi wrote:
> > On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza
> > wrote:
> > > Any write in any display register was causing HW to exit PSR,
> > > masking it to allow more
On Fri, 2018-04-20 at 15:57 -0700, Rodrigo Vivi wrote:
> On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza
> wrote:
> > Any write in any display register was causing HW to exit PSR,
> > masking it to allow more power savings. Writes to pipe related
> > registers will still cause HW
On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza wrote:
> Any write in any display register was causing HW to exit PSR,
> masking it to allow more power savings. Writes to pipe related
> registers will still cause HW to exit PSR.
> This is already masked for PSR2.
>
> Bspec: 7721
On Fri, Apr 20, 2018 at 03:27:56PM -0700, José Roberto de Souza wrote:
> Any write in any display register was causing HW to exit PSR,
> masking it to allow more power savings. Writes to pipe related
> registers will still cause HW to exit PSR.
> This is already masked for PSR2.
This seems a good
Any write in any display register was causing HW to exit PSR,
masking it to allow more power savings. Writes to pipe related
registers will still cause HW to exit PSR.
This is already masked for PSR2.
Bspec: 7721 and 8042
Cc: Rodrigo Vivi
Cc: Dhinakaran Pandiyan