Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-29 Thread Jani Nikula
On Wed, 28 Sep 2016, Manasi Navare wrote: > On Wed, Sep 28, 2016 at 10:38:37AM +0300, Jani Nikula wrote: >> On Wed, 28 Sep 2016, Manasi Navare wrote: >> > On Mon, Sep 26, 2016 at 04:41:27PM +0300, Jani Nikula wrote: >> >> On Fri, 16 Sep 2016,

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-28 Thread Manasi Navare
On Wed, Sep 28, 2016 at 10:14:45AM +0300, Jani Nikula wrote: > On Wed, 28 Sep 2016, Manasi Navare wrote: > > On Tue, Sep 27, 2016 at 04:39:38PM +0300, Jani Nikula wrote: > >> On Mon, 26 Sep 2016, Jani Nikula wrote: > >> > On Fri, 16 Sep

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-28 Thread Manasi Navare
On Wed, Sep 28, 2016 at 10:38:37AM +0300, Jani Nikula wrote: > On Wed, 28 Sep 2016, Manasi Navare wrote: > > On Mon, Sep 26, 2016 at 04:41:27PM +0300, Jani Nikula wrote: > >> On Fri, 16 Sep 2016, Manasi Navare wrote: > >> > While configuring

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-28 Thread Jani Nikula
On Wed, 28 Sep 2016, Manasi Navare wrote: > On Mon, Sep 26, 2016 at 04:41:27PM +0300, Jani Nikula wrote: >> On Fri, 16 Sep 2016, Manasi Navare wrote: >> > While configuring the pipe during modeset, it should use >> > max clock and max lane

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-28 Thread Jani Nikula
On Wed, 28 Sep 2016, Manasi Navare wrote: > On Tue, Sep 27, 2016 at 04:39:38PM +0300, Jani Nikula wrote: >> On Mon, 26 Sep 2016, Jani Nikula wrote: >> > On Fri, 16 Sep 2016, Manasi Navare wrote: >> >> While

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-27 Thread Manasi Navare
On Tue, Sep 27, 2016 at 04:39:38PM +0300, Jani Nikula wrote: > On Mon, 26 Sep 2016, Jani Nikula wrote: > > On Fri, 16 Sep 2016, Manasi Navare wrote: > >> While configuring the pipe during modeset, it should use > >> max clock and max lane

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-27 Thread Manasi Navare
On Mon, Sep 26, 2016 at 04:41:27PM +0300, Jani Nikula wrote: > On Fri, 16 Sep 2016, Manasi Navare wrote: > > While configuring the pipe during modeset, it should use > > max clock and max lane count and reduce the bpp until > > the requested mode rate is less than or

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-27 Thread Jani Nikula
On Mon, 26 Sep 2016, Jani Nikula wrote: > On Fri, 16 Sep 2016, Manasi Navare wrote: >> While configuring the pipe during modeset, it should use >> max clock and max lane count and reduce the bpp until >> the requested mode rate is less than

Re: [Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-26 Thread Jani Nikula
On Fri, 16 Sep 2016, Manasi Navare wrote: > While configuring the pipe during modeset, it should use > max clock and max lane count and reduce the bpp until > the requested mode rate is less than or equal to > available link BW. > This is required to pass DP Compliance.

[Intel-gfx] [PATCH v3 2/6] drm/i915: Remove the link rate and lane count loop in compute config

2016-09-15 Thread Manasi Navare
While configuring the pipe during modeset, it should use max clock and max lane count and reduce the bpp until the requested mode rate is less than or equal to available link BW. This is required to pass DP Compliance. v3: * Add Debug print if requested mode cannot be supported during modeset