Re: [Intel-gfx] [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

2016-04-13 Thread Mika Kuoppala
Abdiel Janulgue writes: > [ text/plain ] > > > On 04/12/2016 04:51 PM, Michał Winiarski wrote: >> We started to use PIPE_CONTROL to write render ring seqno in order to >> combat seqno write vs interrupt generation problems. This was introduced >> by commit 7c17d377374d ("drm/i915: Use ordered seq

Re: [Intel-gfx] [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

2016-04-13 Thread Abdiel Janulgue
On 04/12/2016 04:51 PM, Michał Winiarski wrote: > We started to use PIPE_CONTROL to write render ring seqno in order to > combat seqno write vs interrupt generation problems. This was introduced > by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt > generation on gen8+ execlists

Re: [Intel-gfx] [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

2016-04-12 Thread Dave Gordon
On 12/04/16 14:51, Michał Winiarski wrote: We started to use PIPE_CONTROL to write render ring seqno in order to combat seqno write vs interrupt generation problems. This was introduced by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists"). On gen8+

Re: [Intel-gfx] [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

2016-04-12 Thread Chris Wilson
On Tue, Apr 12, 2016 at 04:58:07PM +0300, Mika Kuoppala wrote: > Michał Winiarski writes: > > > [ text/plain ] > > We started to use PIPE_CONTROL to write render ring seqno in order to > > combat seqno write vs interrupt generation problems. This was introduced > > by commit 7c17d377374d ("drm/i9

Re: [Intel-gfx] [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

2016-04-12 Thread Mika Kuoppala
Michał Winiarski writes: > [ text/plain ] > We started to use PIPE_CONTROL to write render ring seqno in order to > combat seqno write vs interrupt generation problems. This was introduced > by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt > generation on gen8+ execlists"). >

[Intel-gfx] [PATCH v4] drm/i915: Adjust size of PIPE_CONTROL used for gen8 render seqno write

2016-04-12 Thread Michał Winiarski
We started to use PIPE_CONTROL to write render ring seqno in order to combat seqno write vs interrupt generation problems. This was introduced by commit 7c17d377374d ("drm/i915: Use ordered seqno write interrupt generation on gen8+ execlists"). On gen8+ size of PIPE_CONTROL with Post Sync Operatio