On Sat, Nov 11, 2023 at 01:43:20PM +0200, Vinod Govindapillai wrote:
> FIFO underruns are observed when FBC is enabled on plane 2 or
> plane 3. Recommended WA is to update the FBC enabling sequence.
> The plane binding register bits need to be updated separately
> before programming the FBC enable
> -Original Message-
> From: Govindapillai, Vinod
> Sent: Saturday, November 11, 2023 1:43 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Govindapillai, Vinod ; Syrjala, Ville
> ; Saarinen, Jani
> ; Lisovskiy, Stanislav
> ; Kahola, Mika
> Subject: [PATCH v4 1/1] drm/i915/xe2lpd: impleme
FIFO underruns are observed when FBC is enabled on plane 2 or
plane 3. Recommended WA is to update the FBC enabling sequence.
The plane binding register bits need to be updated separately
before programming the FBC enable bit.
Bspec: 74151
Reviewed-by: Mika Kahola #v3
Signed-off-by: Vinod Govinda
