[Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

2016-05-31 Thread Sagar Arun Kamble
On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT expired interrupt (bit 9). Host turbo also updates this register in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists. ARAT timer interrupt is needed in GuC for various features. It also facilitates halting GuC a

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

2016-05-31 Thread Chris Wilson
On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote: > On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT > expired interrupt (bit 9). Host turbo also updates this register > in RPS flows. This patch ensures bit 31 and bit 9 setup by GuC persists. > ARAT timer interru

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

2016-05-31 Thread Matt Roper
On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote: > On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote: > > On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT > > expired interrupt (bit 9). Host turbo also updates this register > > in RPS flows. This patc

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

2016-05-31 Thread Chris Wilson
On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote: > On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote: > > On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote: > > > On Loading, GuC sets PM interrupts routing (bit 31) and clears ARAT > > > expired interrupt (bit 9

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

2016-06-01 Thread Kamble, Sagar A
On 6/1/2016 12:24 PM, Chris Wilson wrote: On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote: On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote: On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote: On Loading, GuC sets PM interrupts routing (bit 31) and clear

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

2016-06-01 Thread Matt Roper
On Wed, Jun 01, 2016 at 07:54:42AM +0100, Chris Wilson wrote: > On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote: > > On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote: > > > On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote: > > > > On Loading, GuC sets PM inte

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

2016-06-02 Thread Kamble, Sagar A
On 6/1/2016 7:59 PM, Matt Roper wrote: On Wed, Jun 01, 2016 at 07:54:42AM +0100, Chris Wilson wrote: On Tue, May 31, 2016 at 04:18:34PM -0700, Matt Roper wrote: On Tue, May 31, 2016 at 09:51:53AM +0100, Chris Wilson wrote: On Tue, May 31, 2016 at 01:58:27PM +0530, Sagar Arun Kamble wrote: O

Re: [Intel-gfx] [PATCH v4 1/1] drm/i915: Update GEN6_PMINTRMSK setup with GuC enabled

2016-06-02 Thread Chris Wilson
On Thu, Jun 02, 2016 at 05:42:08PM +0530, Kamble, Sagar A wrote: > On 6/1/2016 7:59 PM, Matt Roper wrote: > >Hmm, I guess is misunderstood the message thread flow here and didn't > >realize there was another patch necessary as well. I did find that just > >this one patch caused the IGT to start pa