Re: [Intel-gfx] [PATCH v5 09/16] pwm: crc: Fix period changes not having any effect

2020-07-29 Thread Andy Shevchenko
On Fri, Jul 17, 2020 at 03:37:46PM +0200, Hans de Goede wrote: > The pwm-crc code is using 2 different enable bits: > 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) > 2. bit 0 of the BACKLIGHT_EN register > > I strongly suspect that the BACKLIGHT_EN register at address 0x51 really > controls a s

[Intel-gfx] [PATCH v5 09/16] pwm: crc: Fix period changes not having any effect

2020-07-17 Thread Hans de Goede
The pwm-crc code is using 2 different enable bits: 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE) 2. bit 0 of the BACKLIGHT_EN register I strongly suspect that the BACKLIGHT_EN register at address 0x51 really controls a separate output-only GPIO which is connected to the LCD panels backlight-ena