On Thu, 2019-03-07 at 14:30 -0800, Dhinakaran Pandiyan wrote:
> On Thu, 2019-03-07 at 13:57 -0800, Souza, Jose wrote:
> > On Thu, 2019-03-07 at 13:25 -0800, Dhinakaran Pandiyan wrote:
> > > On Tue, 2019-03-05 at 22:47 -0800, José Roberto de Souza wrote:
> > > > If PSR is active when pipe CRC is ena
On Thu, 2019-03-07 at 13:57 -0800, Souza, Jose wrote:
> On Thu, 2019-03-07 at 13:25 -0800, Dhinakaran Pandiyan wrote:
> > On Tue, 2019-03-05 at 22:47 -0800, José Roberto de Souza wrote:
> > > If PSR is active when pipe CRC is enabled the CRC calculations
> > > will
> > > be inhibit by the transitio
On Thu, 2019-03-07 at 13:25 -0800, Dhinakaran Pandiyan wrote:
> On Tue, 2019-03-05 at 22:47 -0800, José Roberto de Souza wrote:
> > If PSR is active when pipe CRC is enabled the CRC calculations will
> > be inhibit by the transition to low power states that PSR brings.
> The MMIO write to enable CR
On Tue, 2019-03-05 at 22:47 -0800, José Roberto de Souza wrote:
> If PSR is active when pipe CRC is enabled the CRC calculations will
> be inhibit by the transition to low power states that PSR brings.
The MMIO write to enable CRCs should bring the hardware out from PSR,
but I can imagine some init
If PSR is active when pipe CRC is enabled the CRC calculations will
be inhibit by the transition to low power states that PSR brings.
So lets for a PSR exit and as soon as pipe CRC is enabled it will
block PSR activation avoid CRC timeouts when running IGT tests.
Cc: Dhinakaran Pandiyan
Cc: Ville
