Re: [Intel-gfx] [PATCH v6] drm/i915/dp: Validate cached link rate and lane count before retraining

Thanks Ville for the review and thanks Jani for pushing this patch. Now we are down to 1 patch to get merged! Regards Manasi On Wed, 12 Apr 2017, Ville Syrjälä wrote: > On Thu, Apr 06, 2017 at 02:00:12PM -0700, Manasi Navare wrote: >> Currently

Re: [Intel-gfx] [PATCH v6] drm/i915/dp: Validate cached link rate and lane count before retraining

On Wed, 12 Apr 2017, Ville Syrjälä wrote: > On Thu, Apr 06, 2017 at 02:00:12PM -0700, Manasi Navare wrote: >> Currently intel_dp_check_link_status() tries to retrain the link if >> Clock recovery or Channel EQ for any of the lanes indicated by >>

Re: [Intel-gfx] [PATCH v6] drm/i915/dp: Validate cached link rate and lane count before retraining

On Thu, Apr 06, 2017 at 02:00:12PM -0700, Manasi Navare wrote: > Currently intel_dp_check_link_status() tries to retrain the link if > Clock recovery or Channel EQ for any of the lanes indicated by > intel_dp->lane_count is not set. However these values cached in intel_dp > structure can be stale

[Intel-gfx] [PATCH v6] drm/i915/dp: Validate cached link rate and lane count before retraining

Currently intel_dp_check_link_status() tries to retrain the link if Clock recovery or Channel EQ for any of the lanes indicated by intel_dp->lane_count is not set. However these values cached in intel_dp structure can be stale if link training has failed for these values during previous modeset.