[Intel-gfx] [PATCH v6] drm/i915: Restore GT performance in headless mode with DMC loaded

2017-12-05 Thread Tvrtko Ursulin
From: Tvrtko Ursulin It seems that the DMC likes to transition between the DC states a lot when there are no connected displays (no active power domains) during command submission. This activity on DC states has a negative impact on the performance of the chip with huge latencies observed in the

Re: [Intel-gfx] [PATCH v6] drm/i915: Restore GT performance in headless mode with DMC loaded

2017-12-05 Thread Chris Wilson
Quoting Tvrtko Ursulin (2017-12-05 13:28:54) > From: Tvrtko Ursulin > > It seems that the DMC likes to transition between the DC states a lot when > there are no connected displays (no active power domains) during command > submission. > > This activity on DC states has a negative impact on the

Re: [Intel-gfx] [PATCH v6] drm/i915: Restore GT performance in headless mode with DMC loaded

2017-12-08 Thread Imre Deak
On Tue, Dec 05, 2017 at 01:35:11PM +, Chris Wilson wrote: > Quoting Tvrtko Ursulin (2017-12-05 13:28:54) > > From: Tvrtko Ursulin > > > > It seems that the DMC likes to transition between the DC states a lot when > > there are no connected displays (no active power domains) during command > >