[Intel-gfx] [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT

2019-06-27 Thread Lionel Landwerlin
CFL:C0+ changed the status of those registers which are now blacklisted by default. This is breaking a number of CTS tests on GL & Vulkan : KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations (GL) dEQP-VK.query_pool.statistics_query.fragment_shader_invocatio

Re: [Intel-gfx] [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT

2019-06-27 Thread Chris Wilson
Quoting Lionel Landwerlin (2019-06-27 10:01:15) > CFL:C0+ changed the status of those registers which are now > blacklisted by default. > > This is breaking a number of CTS tests on GL & Vulkan : > > > KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragment_shader_invocations > (GL)

Re: [Intel-gfx] [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT

2019-06-27 Thread Lionel Landwerlin
On 27/06/2019 14:53, Chris Wilson wrote: Quoting Lionel Landwerlin (2019-06-27 10:01:15) CFL:C0+ changed the status of those registers which are now blacklisted by default. This is breaking a number of CTS tests on GL & Vulkan : KHR-GL45.pipeline_statistics_query_tests_ARB.functional_fragm

Re: [Intel-gfx] [PATCH v6 2/3] drm/i915: whitelist PS_(DEPTH|INVOCATION)_COUNT

2019-06-27 Thread Chris Wilson
Quoting Lionel Landwerlin (2019-06-28 00:53:09) > On 27/06/2019 14:53, Chris Wilson wrote: > > Magic! As we can't rely on our selftests to verify that this allows > > access from user batches, could you poke Anuj for another tested by? > > -Chris > > > I'll let Anuj answer. > > Do I need Cc: sta..