Re: [Intel-gfx] [PATCH v6 2/8] drm/i915/bxt: IPC WA for Broxton

2016-12-01 Thread Lankhorst, Maarten
Hey, Mahesh Kumar schreef op ma 28-11-2016 om 18:37 [+0530]: > Hi, > > Will keep WA number in commit message/WA location. > thanks, Sounds good, with that fixed patches 1-5 and 7 look good to me. I think patch 6 will no longer be required since the workaround status will also be kept inside inte

Re: [Intel-gfx] [PATCH v6 2/8] drm/i915/bxt: IPC WA for Broxton

2016-11-28 Thread Mahesh Kumar
Hi, Will keep WA number in commit message/WA location. thanks, Regards, -Mahesh On Thursday 24 November 2016 06:21 PM, Lankhorst, Maarten wrote: Mahesh Kumar schreef op do 24-11-2016 om 09:31 [+0530]: If IPC is enabled in BXT, display underruns are observed. WA: The Line Time programmed in t

Re: [Intel-gfx] [PATCH v6 2/8] drm/i915/bxt: IPC WA for Broxton

2016-11-24 Thread Lankhorst, Maarten
Mahesh Kumar schreef op do 24-11-2016 om 09:31 [+0530]: > If IPC is enabled in BXT, display underruns are observed. > WA: The Line Time programmed in the WM_LINETIME register should be > half of the actual calculated Line Time. > > Programmed Line Time = 1/2*Calculated Line Time > > Signed-off-by

[Intel-gfx] [PATCH v6 2/8] drm/i915/bxt: IPC WA for Broxton

2016-11-23 Thread Mahesh Kumar
If IPC is enabled in BXT, display underruns are observed. WA: The Line Time programmed in the WM_LINETIME register should be half of the actual calculated Line Time. Programmed Line Time = 1/2*Calculated Line Time Signed-off-by: Mahesh Kumar Reviewed-by: Paulo Zanoni --- drivers/gpu/drm/i915/i