On 4/18/2018 9:45 AM, Oscar Mateo wrote:
On 4/18/2018 9:38 AM, Chris Wilson wrote:
Quoting Oscar Mateo (2018-04-18 17:30:41)
On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
+ /*
+ * HW expects MCR to be programed to a enabled slice/subslice
pair
+ * before any MMIO read into sli
On 4/18/2018 9:38 AM, Chris Wilson wrote:
Quoting Oscar Mateo (2018-04-18 17:30:41)
On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
+ /*
+ * HW expects MCR to be programed to a enabled slice/subslice pair
+ * before any MMIO read into slice/subslice register
+ */
The comment ab
Quoting Oscar Mateo (2018-04-18 17:30:41)
>
>
> On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
> > + /*
> > + * HW expects MCR to be programed to a enabled slice/subslice pair
> > + * before any MMIO read into slice/subslice register
> > + */
>
> The comment above makes more sense
On 4/17/2018 3:58 PM, Yunwei Zhang wrote:
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value wil
WaProgramMgsrForCorrectSliceSpecificMmioReads dictate that before any MMIO
read into Slice/Subslice specific registers, MCR packet control
register(0xFDC) needs to be programmed to point to any enabled
slice/subslice pair. Otherwise, incorrect value will be returned.
However, that means each subse
