Re: [Intel-gfx] [PATCH v9 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

2015-08-05 Thread Michel Thierry
On 8/5/2015 4:46 PM, Daniel Vetter wrote: On Mon, Aug 03, 2015 at 09:53:27AM +0100, Michel Thierry wrote: @@ -735,12 +736,21 @@ static void gen8_ppgtt_clear_range(struct i915_address_space *vm, { struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base

Re: [Intel-gfx] [PATCH v9 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

2015-08-05 Thread Daniel Vetter
On Mon, Aug 03, 2015 at 09:53:27AM +0100, Michel Thierry wrote: > When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map > Level 4 (PML4), before it selects which Page Directory Pointer (PDP) > it will write to. > > Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/

Re: [Intel-gfx] [PATCH v9 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

2015-08-03 Thread Goel, Akash
Reviewed the patch & it looks fine. Reviewed-by: "Akash Goel " On 8/3/2015 2:23 PM, Michel Thierry wrote: When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map Level 4 (PML4), before it selects which Page Directory Pointer (PDP) it will write to. Similarly, gen8_ppgtt_clear

[Intel-gfx] [PATCH v9 10/19] drm/i915/gen8: Add 4 level support in insert_entries and clear_range

2015-08-03 Thread Michel Thierry
When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map Level 4 (PML4), before it selects which Page Directory Pointer (PDP) it will write to. Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range. This patch was inspired by Ben's "Depend exclusively on map and