[Intel-gfx] [PATCH v9 6/8] drm/i915: WA for platforms with double buffered address update enable bit

2020-09-16 Thread Karthik B S
In Gen 9 and Gen 10 platforms, async address update enable bit is double buffered. Due to this, during the transition from async flip to sync flip we have to wait until this bit is updated before continuing with the normal commit for sync flip. v9: -Rename skl_toggle_async_sync() to skl_disable_as

Re: [Intel-gfx] [PATCH v9 6/8] drm/i915: WA for platforms with double buffered address update enable bit

2020-09-18 Thread Ville Syrjälä
On Wed, Sep 16, 2020 at 08:38:22PM +0530, Karthik B S wrote: > In Gen 9 and Gen 10 platforms, async address update enable bit is > double buffered. Due to this, during the transition from async flip > to sync flip we have to wait until this bit is updated before continuing > with the normal commit

Re: [Intel-gfx] [PATCH v9 6/8] drm/i915: WA for platforms with double buffered address update enable bit

2020-09-21 Thread Karthik B S
On 9/18/2020 5:24 PM, Ville Syrjälä wrote: On Wed, Sep 16, 2020 at 08:38:22PM +0530, Karthik B S wrote: In Gen 9 and Gen 10 platforms, async address update enable bit is double buffered. Due to this, during the transition from async flip to sync flip we have to wait until this bit is updated b