On Tue, 20 Dec 2022, "Murthy, Arun R" wrote:
>> -Original Message-
>> From: Nikula, Jani
>> Sent: Tuesday, December 20, 2022 9:33 PM
>> To: Murthy, Arun R ; intel-
>> g...@lists.freedesktop.org; ville.syrj...@linux.intel.com; Deak, Imre
>>
>> Subject: RE: [PATCHv6] drm/i915/dp: change au
> -Original Message-
> From: Nikula, Jani
> Sent: Tuesday, December 20, 2022 9:33 PM
> To: Murthy, Arun R ; intel-
> g...@lists.freedesktop.org; ville.syrj...@linux.intel.com; Deak, Imre
>
> Subject: RE: [PATCHv6] drm/i915/dp: change aux_ctl reg read to polling read
>
> On Mon, 19 Dec 20
On Mon, 19 Dec 2022, "Murthy, Arun R" wrote:
> Any comments?
>From #intel-gfx:
bashing the hw for 500 usec seems a bit harsh
Which is true. The default for intel_de_wait_for_register() is 2
us. Should probably stick to that.
BR,
Jani.
>
> Thanks and Regards,
> Arun R Murthy
> --
Any comments?
Thanks and Regards,
Arun R Murthy
> -Original Message-
> From: Murthy, Arun R
> Sent: Thursday, December 15, 2022 4:44 PM
> To: intel-gfx@lists.freedesktop.org; ville.syrj...@linux.intel.com; Nikula,
> Jani
> ; Deak, Imre
> Cc: Murthy, Arun R
> Subje
The busy timeout logic checks for the AUX BUSY, then waits for the
timeout period and then after timeout reads the register for BUSY or
Success.
Instead replace interrupt with polling so as to read the AUX CTL
register often before the timeout period. Looks like there might be some
issue with inter
> -Original Message-
> From: Nikula, Jani
> Sent: Thursday, December 15, 2022 4:00 PM
> To: Murthy, Arun R ; intel-
> g...@lists.freedesktop.org; ville.syrj...@linux.intel.com; Deak, Imre
>
> Cc: Murthy, Arun R
> Subject: Re: [PATCHv6] drm/i915/dp: change aux_ctl reg read to polling read
On Thu, 15 Dec 2022, Arun R Murthy wrote:
> The busy timeout logic checks for the AUX BUSY, then waits for the
> timeout period and then after timeout reads the register for BUSY or
> Success.
> Instead replace interrupt with polling so as to read the AUX CTL
> register often before the timeout pe
The busy timeout logic checks for the AUX BUSY, then waits for the
timeout period and then after timeout reads the register for BUSY or
Success.
Instead replace interrupt with polling so as to read the AUX CTL
register often before the timeout period. Looks like there might be some
issue with inter
