On Wed, 28 Mar 2012 02:59:26 -0700
Andi Kleen wrote:
> Ben Widawsky writes:
> >
> > 1. Handle cache line going bad interrupt.
> >
>
> Never use global n without timeout for corrected errors, you would
> need a leaky bucket with a suitable timeout.
As I understand electrons (which is not very
On Wed, 28 Mar 2012 10:26:52 -0700
Jesse Barnes wrote:
> On Tue, 27 Mar 2012 07:19:43 -0700
> Ben Widawsky wrote:
>
> > I wanted to run this by folks before I start doing any actual work.
> >
> > This is primarily for GPGPU, or perhaps *really* accurate rendering
> > requirements.
> >
> > IVB
On Tue, 27 Mar 2012 07:19:43 -0700
Ben Widawsky wrote:
> I wanted to run this by folks before I start doing any actual work.
>
> This is primarily for GPGPU, or perhaps *really* accurate rendering
> requirements.
>
> IVB+ has an interrupt to tell us when a cacheline seems to be going bad.
> The
On Tue, Mar 27, 2012 at 08:09:31AM -0700, Ben Widawsky wrote:
> On Tue, 27 Mar 2012 16:50:39 +0200
> Daniel Vetter wrote:
>
> > On Tue, Mar 27, 2012 at 07:19:43AM -0700, Ben Widawsky wrote:
> > > I wanted to run this by folks before I start doing any actual work.
> > >
> > > This is primarily fo
On Tue, 27 Mar 2012 16:50:39 +0200
Daniel Vetter wrote:
> On Tue, Mar 27, 2012 at 07:19:43AM -0700, Ben Widawsky wrote:
> > I wanted to run this by folks before I start doing any actual work.
> >
> > This is primarily for GPGPU, or perhaps *really* accurate rendering
> > requirements.
> >
> > I
On Tue, Mar 27, 2012 at 07:19:43AM -0700, Ben Widawsky wrote:
> I wanted to run this by folks before I start doing any actual work.
>
> This is primarily for GPGPU, or perhaps *really* accurate rendering
> requirements.
>
> IVB+ has an interrupt to tell us when a cacheline seems to be going bad.
On Tue, 27 Mar 2012 07:19:43 -0700, Ben Widawsky wrote:
> Any feedback is highly appreciated. I couldn't really find much
> precedent for doing this in other drivers, so pointers to similar
> things would also be highly welcome.
badblocks and badram (memmap) both seem to be similar situations. A
I wanted to run this by folks before I start doing any actual work.
This is primarily for GPGPU, or perhaps *really* accurate rendering
requirements.
IVB+ has an interrupt to tell us when a cacheline seems to be going bad.
There is also a mechanism to remap the bad cachelines. The
implementation
