On Thu, Nov 26, 2020 at 03:09:50PM +0530, Anshuman Gupta wrote:
> On 2020-11-25 at 18:24:44 +0200, Imre Deak wrote:
> > +Ville.
> Hi Ville ,
> Let me provide you some context over the issue which requires your input.
> TGL on chorome OS has observed some display glitches when brightness is being
On 2020-11-25 at 18:24:44 +0200, Imre Deak wrote:
> +Ville.
Hi Ville ,
Let me provide you some context over the issue which requires your input.
TGL on chorome OS has observed some display glitches when brightness is being
updated
at very fast rate. This has surfaced out two issue.
1. Getting the
+Ville.
On Wed, Nov 25, 2020 at 01:16:27PM +0530, Anshuman Gupta wrote:
> On 2020-11-24 at 18:44:06 +0200, Imre Deak wrote:
> > On Tue, Nov 24, 2020 at 03:28:47PM +0530, Anshuman Gupta wrote:
> > > Platforms with South Display Engine on PCH, doesn't
> > > require to get/put the AUX power domain
On 2020-11-24 at 18:44:06 +0200, Imre Deak wrote:
> On Tue, Nov 24, 2020 at 03:28:47PM +0530, Anshuman Gupta wrote:
> > Platforms with South Display Engine on PCH, doesn't
> > require to get/put the AUX power domain in order to
> > access PPS register because PPS registers are always on
> > with
On Tue, Nov 24, 2020 at 03:28:47PM +0530, Anshuman Gupta wrote:
> Platforms with South Display Engine on PCH, doesn't
> require to get/put the AUX power domain in order to
> access PPS register because PPS registers are always on
> with South display on PCH.
>
> Cc: Imre Deak
> Cc:
>
Platforms with South Display Engine on PCH, doesn't
require to get/put the AUX power domain in order to
access PPS register because PPS registers are always on
with South display on PCH.
Cc: Imre Deak
Cc:
Signed-off-by: Anshuman Gupta
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drivers/gpu/drm/i915/display/intel_dp.c | 13
