Master irq register is accessed twice every irq handling, then trapped
to SOS very frequently. Optimize it by moving master irq register
to share page, writing don't need be trapped.
When need enable irq to let SOS inject irq timely, use another pvmmio
register to achieve this purpose. So avoid one trap when we disable
master irq.
Use PVMMIO_MASTER_IRQ to control this level of pvmmio optimization.
Signed-off-by: Xiaolin Zhang <xiaolin.zh...@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 29 +++++++++++++++++++++++------
drivers/gpu/drm/i915/i915_params.h | 2 +-
drivers/gpu/drm/i915/i915_pvinfo.h | 3 ++-
3 files changed, 26 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 2e24227..f911ed1 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2901,7 +2901,10 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
if (!master_ctl)
return IRQ_NONE;
- I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
+ if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ))
+ dev_priv->shared_page->disable_irq = 1;
+ else
+ I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
/* Find, clear, then process each source of interrupt */
gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir);
@@ -2913,7 +2916,12 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
enable_rpm_wakeref_asserts(dev_priv);
}
- I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+ if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ)) {
+ dev_priv->shared_page->disable_irq = 0;
+ __raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+ } else {
+ I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+ }
gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
@@ -3598,8 +3606,12 @@ static void gen8_irq_reset(struct drm_device *dev)
struct drm_i915_private *dev_priv = to_i915(dev);
int pipe;
- I915_WRITE(GEN8_MASTER_IRQ, 0);
- POSTING_READ(GEN8_MASTER_IRQ);
+ if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ)) {
+ dev_priv->shared_page->disable_irq = 1;
+ } else {
+ I915_WRITE(GEN8_MASTER_IRQ, 0);
+ POSTING_READ(GEN8_MASTER_IRQ);
+ }
gen8_gt_irq_reset(dev_priv);
@@ -4244,8 +4256,13 @@ static int gen8_irq_postinstall(struct drm_device *dev)
if (HAS_PCH_SPLIT(dev_priv))
ibx_irq_postinstall(dev);
- I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
- POSTING_READ(GEN8_MASTER_IRQ);
+ if (PVMMIO_LEVEL_ENABLE(dev_priv, PVMMIO_MASTER_IRQ)) {
+ dev_priv->shared_page->disable_irq = 0;
+ __raw_i915_write32(dev_priv, vgtif_reg(check_pending_irq), 1);
+ } else {
+ I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
+ POSTING_READ(GEN8_MASTER_IRQ);
+ }
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_params.h
b/drivers/gpu/drm/i915/i915_params.h
index 6c81c87..bfc30a0 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -69,7 +69,7 @@
param(bool, enable_dp_mst, true) \
param(bool, enable_dpcd_backlight, false) \
param(bool, enable_gvt, false) \
- param(int, enable_pvmmio, PVMMIO_ELSP_SUBMIT)
+ param(int, enable_pvmmio, PVMMIO_ELSP_SUBMIT | PVMMIO_MASTER_IRQ)
#define MEMBER(T, member, ...) T member;
struct i915_params {
diff --git a/drivers/gpu/drm/i915/i915_pvinfo.h
b/drivers/gpu/drm/i915/i915_pvinfo.h
index ab839a7..60183c7 100644
--- a/drivers/gpu/drm/i915/i915_pvinfo.h
+++ b/drivers/gpu/drm/i915/i915_pvinfo.h
@@ -143,8 +143,9 @@ struct vgt_if {
u32 lo;
u32 hi;
} shared_page_gpa;
+ u32 check_pending_irq;
- u32 rsv7[0x200 - 27]; /* pad to one page */
+ u32 rsv7[0x200 - 28]; /* pad to one page */
} __packed;
#define vgtif_reg(x) \
--
1.8.3.1
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