Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
and HDCP2_AUTH_STREAM register in i915_reg header.

Cc: Ramalingam C <ramalinga...@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gu...@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1a027b1ec5aa..d4995389cecd 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9857,6 +9857,7 @@ enum skl_power_gate {
                                          _PORTD_HDCP2_BASE, \
                                          _PORTE_HDCP2_BASE, \
                                          _PORTF_HDCP2_BASE) + (x))
+
 #define PORT_HDCP2_AUTH(port)          _PORT_HDCP2_BASE(port, 0x98)
 #define _TRANSA_HDCP2_AUTH             0x66498
 #define _TRANSB_HDCP2_AUTH             0x66598
@@ -9896,6 +9897,35 @@ enum skl_power_gate {
                                         TRANS_HDCP2_STATUS(trans) : \
                                         PORT_HDCP2_STATUS(port))
 
+#define PORT_HDCP2_STREAM_STATUS(port)         _PORT_HDCP2_BASE(port, 0xC0)
+#define _TRANSA_HDCP2_STREAM_STATUS            0x664C0
+#define _TRANSB_HDCP2_STREAM_STATUS            0x665C0
+#define TRANS_HDCP2_STREAM_STATUS(trans)       _MMIO_TRANS(trans, \
+                                                   
_TRANSA_HDCP2_STREAM_STATUS, \
+                                                   _TRANSB_HDCP2_STREAM_STATUS)
+#define   STREAM_ENCRYPTION_STATUS     BIT(31)
+#define   STREAM_TYPE_STATUS           BIT(30)
+#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
+                                       (INTEL_GEN(dev_priv) >= 12 ? \
+                                        TRANS_HDCP2_STREAM_STATUS(trans) : \
+                                        PORT_HDCP2_STREAM_STATUS(port))
+
+#define _PORTA_HDCP2_AUTH_STREAM               0x66F00
+#define _PORTB_HDCP2_AUTH_STREAM               0x66F04
+#define PORT_HDCP2_AUTH_STREAM(port)   _MMIO_PORT(port, \
+                                                  _PORTA_HDCP2_AUTH_STREAM, \
+                                                  _PORTB_HDCP2_AUTH_STREAM)
+#define _TRANSA_HDCP2_AUTH_STREAM              0x66F00
+#define _TRANSB_HDCP2_AUTH_STREAM              0x66F04
+#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
+                                                   _TRANSA_HDCP2_AUTH_STREAM, \
+                                                   _TRANSB_HDCP2_AUTH_STREAM)
+#define   AUTH_STREAM_TYPE             BIT(31)
+#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
+                                       (INTEL_GEN(dev_priv) >= 12 ? \
+                                        TRANS_HDCP2_AUTH_STREAM(trans) : \
+                                        PORT_HDCP2_AUTH_STREAM(port))
+
 /* Per-pipe DDI Function Control */
 #define _TRANS_DDI_FUNC_CTL_A          0x60400
 #define _TRANS_DDI_FUNC_CTL_B          0x61400
-- 
2.26.2

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