Re: [Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-10-12 Thread Imre Deak
On ma, 2015-08-03 at 21:55 +0530, Animesh Manna wrote: > Mmio register access after dc6/dc5 entry is not allowed when > DC6 power states are enabled according to bspec (bspec-id 0527), > so enabling dc6 as the last call in suspend flow. The MMIO range BSpec-ID 0527 refers to is the DMC MMIO range.

Re: [Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-08-06 Thread Daniel Vetter
On Thu, Aug 06, 2015 at 08:08:58PM +0530, Animesh Manna wrote: > > > On 8/6/2015 6:48 PM, Daniel Vetter wrote: > >On Thu, Aug 06, 2015 at 02:47:22PM +0530, Animesh Manna wrote: > >> > >>On 8/5/2015 2:35 PM, Daniel Vetter wrote: > >>>On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote: >

Re: [Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-08-06 Thread Animesh Manna
On 8/6/2015 6:48 PM, Daniel Vetter wrote: On Thu, Aug 06, 2015 at 02:47:22PM +0530, Animesh Manna wrote: On 8/5/2015 2:35 PM, Daniel Vetter wrote: On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote: Mmio register access after dc6/dc5 entry is not allowed when DC6 power states are

Re: [Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-08-06 Thread Daniel Vetter
On Thu, Aug 06, 2015 at 02:47:22PM +0530, Animesh Manna wrote: > > > On 8/5/2015 2:35 PM, Daniel Vetter wrote: > >On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote: > >>Mmio register access after dc6/dc5 entry is not allowed when > >>DC6 power states are enabled according to bspec (bs

Re: [Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-08-06 Thread Animesh Manna
On 8/5/2015 2:35 PM, Daniel Vetter wrote: On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote: Mmio register access after dc6/dc5 entry is not allowed when DC6 power states are enabled according to bspec (bspec-id 0527), so enabling dc6 as the last call in suspend flow. v1: Initial

Re: [Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-08-05 Thread Daniel Vetter
On Tue, Aug 04, 2015 at 04:55:59PM +0530, Sunil Kamath wrote: > On Monday 03 August 2015 09:55 PM, Animesh Manna wrote: > >Mmio register access after dc6/dc5 entry is not allowed when > >DC6 power states are enabled according to bspec (bspec-id 0527), > >so enabling dc6 as the last call in suspend

Re: [Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-08-05 Thread Daniel Vetter
On Mon, Aug 03, 2015 at 09:55:33PM +0530, Animesh Manna wrote: > Mmio register access after dc6/dc5 entry is not allowed when > DC6 power states are enabled according to bspec (bspec-id 0527), > so enabling dc6 as the last call in suspend flow. > > v1: Initial version. > > v2: commit message upda

Re: [Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-08-04 Thread Sunil Kamath
On Monday 03 August 2015 09:55 PM, Animesh Manna wrote: Mmio register access after dc6/dc5 entry is not allowed when DC6 power states are enabled according to bspec (bspec-id 0527), so enabling dc6 as the last call in suspend flow. v1: Initial version. v2: commit message updated based on commen

[Intel-gfx] [SKL-DMC-BUGFIX 2/5] drm/i915/skl: Making DC6 entry is the last call in suspend flow.

2015-08-03 Thread Animesh Manna
Mmio register access after dc6/dc5 entry is not allowed when DC6 power states are enabled according to bspec (bspec-id 0527), so enabling dc6 as the last call in suspend flow. v1: Initial version. v2: commit message updated based on comment from Vathsala. Cc: Daniel Vetter Cc: Damien Lespiau C