Implement Plane Gamma on ICL.
Signed-off-by: Uma Shankar <uma.shan...@intel.com>
---
drivers/gpu/drm/i915/intel_color.c | 75 ++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 504c046..22790b4 100644
--- a/drivers/gpu/drm/i915/intel_color.c
+++ b/drivers/gpu/drm/i915/intel_color.c
@@ -692,10 +692,85 @@ static void icl_load_plane_degamma_lut(const struct
drm_plane_state *state,
}
}
+static void icl_load_plane_gamma_lut(const struct drm_plane_state *state,
+ u32 offset)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->plane->dev);
+ enum pipe pipe = to_intel_plane(state->plane)->pipe;
+ enum plane_id plane = to_intel_plane(state->plane)->id;
+ u32 i, lut_size;
+
+ lut_size = 32;
+ if (icl_is_hdr_plane(dev_priv, plane)) {
+ if (state->degamma_lut) {
+ struct drm_color_lut_ext *lut =
+ (struct drm_color_lut_ext
*)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++) {
+ u64 word =
drm_color_lut_extract_ext(lut[i].red, 24);
+ u32 lut_val = (word & 0x7ffffffff) >> 8;
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i), lut_val);
+ }
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ drm_color_lut_extract_ext(lut[i].red, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ drm_color_lut_extract_ext(lut[i].green, 24));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ drm_color_lut_extract_ext(lut[i].blue, 24));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe,
plane, i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 1),
+ (1 << 24) - 1);
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 2),
+ (1 << 24) - 1);
+ }
+ } else {
+ if (state->degamma_lut) {
+ struct drm_color_lut *lut =
+ (struct drm_color_lut *)state->gamma_lut->data;
+
+ for (i = 0; i < lut_size; i++)
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i),
+ lut[i].green);
+
+ /* Program the max register to clamp values > 1.0. */
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ } else {
+ for (i = 0; i < lut_size; i++) {
+ u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1);
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane,
i), v);
+ }
+
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 0),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 1),
+ (1 << 16));
+ I915_WRITE(PLANE_PRE_CSC_GAMC_DATA(pipe, plane, 2),
+ (1 << 16));
+ }
+ }
+}
+
/* Loads the palette/gamma unit for the CRTC on Gen11+. */
static void icl_load_plane_luts(const struct drm_plane_state *state)
{
icl_load_plane_degamma_lut(state, 0);
+ icl_load_plane_gamma_lut(state, 0);
}
static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
