Squashes the patchset to a single patch to avoid any
build failure.
Anshuman Gupta (1):
drm/i915/dg1: Adjust the AUDIO power domain
drivers/gpu/drm/i915/display/intel_audio.c| 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c
avoid build failure.
Cc: Ville Syrjälä
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Imre Deak
Reviewed-by: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_audio.c| 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display
:
- removed RKL from comment and simplified condition. [Rodrigo]
Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
platforms")
Cc: Matt Roper
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
Reviewed-by: Rodrigo Vivi
---
.../drm/i9
:
- removed RKL from comment and simplified condition. [Rodrigo]
Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
platforms")
Cc: Matt Roper
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
Reviewed-by: Rodrigo Vivi
---
.../drm/i9
failing.
Anshuman Gupta (1):
drm/i915: Tweaked Wa_14010685332 for all PCHs
.../drm/i915/display/intel_display_power.c| 16 +++---
drivers/gpu/drm/i915/i915_irq.c | 21 ---
2 files changed, 8 insertions(+), 29 deletions(-)
--
2.26.2
:
- removed RKL from comment and simplified condition. [Rodrigo]
Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
platforms")
Cc: Matt Roper
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
Reviewed-by: Rodrigo Vivi
---
.../drm/i9
NOTRUN -> [DMESG-WARN][1]
>[1]:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20792/fi-rkl-guc/igt@core_hotunp...@unbind-rebind.html
Hi Lakshmi ,
Above CI BAT failure is a unrealted failure(not realted to display), it
seems related to core power.
;
> + struct intel_hdcp *hdcp = &connector->hdcp;
> int ret = 0, i, tries = 3;
>
> for (i = 0; i < tries && !dig_port->hdcp_auth_status; i++) {
> ret = hdcp2_authenticate_sink(connector);
> if (!ret) {
&g
fset to account for RxInfo being read
v5 looks good to me
Reviewed-by: Anshuman Gupta
>
> Changes in v4:
> - rebase and edit commit message
>
> Changes in v3:
> - remove comment
>
> Changes in v2:
> - remove unnecessary moving of drm_i915_private from patch 1
>
>
]
removed pointless code. [Ville]
v8 (Daniele): update PXP check
v9: move decrypt check after icl_check_nv12_planes() when overlays
have fb set (Juston)
Cc: Bommu Krishnaiah
Cc: Huang Sean Z
Cc: Gaurav Kumar
Cc: Ville Syrjälä
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo
): update pxp_is_borked check.
v5: rebase on top of v9 plane decryption moving the decrypt check
(Juston)
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Juston Li
Reviewed-by: Rodrigo Vivi
---
drivers/gpu
:
> https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_20792/shard-skl4/igt@kms_frontbuffer_track...@psr-rgb565-draw-blt.html
Hi Lakshmi,
This CI IGT failure is on unrelated platfrom and not realted to this patch.
Pushed to drm-intel-next, while pushing fixed a checkpatch
"W
get cpu_trancoder from intel_psr, therefore we don't need to
> pass intel_crtc_state to this function.
>
> Cc: José Roberto de Souza
> Signed-off-by: Gwan-gyeong Mun
> Signed-off-by: Matt Roper
Reviewed-by: Anshuman Gupta
> ---
> drivers/gpu/drm/i915/display/intel_psr.c
> [INCOMPLETE][1] +2 similar issues
> [1]: None
Above failures not related to HDCP failures.
Pushed the series to drm-intel-next.
Thanks for patch.
Br,
Anshuman Gupta.
>
>
> New tests
> -
>
> New tests have been introduced between CI_DRM_10537_full and
>
PCHs used on
> > gen11 platforms") Cc: Matt Roper
> > Cc: Rodrigo Vivi
> > Cc: Imre Deak
> > Signed-off-by: Anshuman Gupta
> > ---
> >
> > .../drm/i915/display/intel_display_power.c| 16 +++---
> > drivers/gpu/drm/i915/i915_irq.
This revision has fixed review comment from Imre on RFC patch.
https://patchwork.freedesktop.org/series/90827/
Anshuman Gupta (3):
drm/i915/dg1: Adjust the AUDIO power domain
drm/i915/display: Use AUDIO_MMIO for crtc power domain mask
drm/i915/audio: Use AUDIO_PLAYBACK power domain
This revision has fixed review comment from Imre on RFC patch.
https://patchwork.freedesktop.org/series/90827/
Anshuman Gupta (3):
drm/i915/dg1: Adjust the AUDIO power domain
drm/i915/display: Use AUDIO_MMIO for crtc power domain mask
drm/i915/audio: Use AUDIO_PLAYBACK power domain
Vehmanen
Cc: Uma Shankar
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers
Use POWER_DOMAIN_AUDIO_PLAYBACK to enable/disable
display audio codec power in intel_display_power_{get, put}
v1: Changes since RFC
- changed power domain names. [Imre]
Cc: Kai Vehmanen
Cc: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_audio.c | 4 ++--
1
TBT from DG1
power well and PW_3 power domains. [Imre]
- Fixed the order of powe wells , power domains and its
registration. [Imre]
Cc: Ville Syrjälä
Cc: Kai Vehmanen
Cc: Uma Shankar
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 232
Adding HDCP support over DP MST for Display13 Platforms.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
b/drivers/gpu/drm/i915/display/intel_dp_mst.c
Earlier HDCP over MST support was added for TGL Platform.
Extending it to all future platfroms.
v2:
- Remove the platform check and commit log changes. [Jani]
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ---
1 file changed, 4 insertions(+), 7
Extend i915_lpsp_capability sysfs to xelpd and future platforms.
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_debugfs.c
b/drivers/gpu
:
- removed RKL from comment and simplified condition. [Rodrigo]
Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
platforms")
Cc: Matt Roper
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
Reviewed-by: Rodrigo Vivi
---
.../drm/i9
Extend i915_lpsp_capability debugfs to DG2,ADLP and future platforms.
v2: commit log modification.
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display_debugfs.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
HDCP DP 2.2 errata is part of HDCP DP 2.3 specs
as well.
Anshuman Gupta (2):
drm/i915/hdcp: Add DP HDCP2.2 timeout to read entire msg
drm/hdcp: DP HDCP2.2 errata LC_Send_L_Prime=16
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 45 ++--
include/drm/drm_hdcp.h
authentication
in case it timedout to read entire msg.
https://www.digital-cp.com/sites/default/files/HDCP%202_2_DisplayPort_Errata_v3_0.pdf
v2:
- Removed redundant variable msg_can_timedout. [Ankit]
Cc: Ramalingam C
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 45
Fix LC_Send_L_Prime message timeout to 16 as documented
in DP HDCP 2.2 errata page 3.
https://www.digital-cp.com/sites/default/files/HDCP%202_2_DisplayPort_Errata_v3_0.pdf
Cc: Ramalingam C
Reviewed-by: Ankit Nautiyal
Signed-off-by: Anshuman Gupta
---
include/drm/drm_hdcp.h | 2 +-
1 file
: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
platforms")
Cc: Matt Roper
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 18 +---
drivers/gpu/drm/i915/i915_irq.c | 21 --
:
- removed RKL from comment and simplified condition. [Rodrigo]
Fixes: b896898c7369 ("drm/i915: Tweaked Wa_14010685332 for PCHs used on gen11
platforms")
Cc: Matt Roper
Cc: Rodrigo Vivi
Cc: Imre Deak
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power
Fix static analysis tool uninitialized symbol error.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display
Fix static analysis tool uninitialized symbol error.
v2:
- use ktime_set(0, 0) instead to initialize to zero. [Ankit]
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 2 +-
1 file changed, 1 insertion
Syrjälä
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 3 ++
drivers/gpu/drm/i915/display/intel_display.c | 5 +++
.../drm/i915/display/intel_display_types.h| 3 ++
.../drm/i915/display/skl_universal_plane.c| 32
When protected sufaces has flipped and pxp session is disabled,
display black pixels by using plane color CTM correction.
v2:
- Display black pixels in aysnc flip too.
Cc: Ville Syrjälä
Cc: Gaurav Kumar
Cc: Shankar Uma
Signed-off-by: Anshuman Gupta
Signed-off-by: Daniele Ceraolo Spurio
49233
B.Spec: 49231
Cc: Ville Syrjälä
Cc: Kai Vehmanen
Cc: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm
This patch series adds new tests to validate Display C states.
DC states like DC5 and DC6 are validated during PSR entry/exit
and during DPMS on/off cycle.
Sending new revision of patch series after addressing review comments.
Jyoti Yadav (5):
lib/igt_pm: Moves Dmc_loaded() function into library
: Anshuman Gupta
---
lib/igt_pm.c | 28
lib/igt_pm.h | 1 +
tests/pm_rpm.c | 17 +
3 files changed, 30 insertions(+), 16 deletions(-)
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 4902723..8b87c58 100644
--- a/lib/igt_pm.c
+++ b/lib/igt_pm.c
@@ -38,6
From: Jyoti Yadav
This patch add subtest to check DC6 entry on PSR for the supported
platforms.
v2: Rename the subtest with more meaningful name.
v3: Rebased.
v4: Rebased and addressed review comment.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/pm_dc.c | 13
From: Jyoti Yadav
Added new subtest for DC5 entry during DPMS on/off cycle.
During DPMS on/off cycle DC5 counter is incremented.
v2: Rename the subtest with meaningful name.
v3: Rebased.
v4: Addressed review comments.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests
.
v3: one second timeout is introduced to read DC counters.
Skip the subtest if counters are not available for that platform.
v4: Rebased, addressed the review comment and spell correction.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/Makefile.sources | 1 +
tests
From: Jyoti Yadav
Added new subtest for DC6 entry during DPMS on/off cycle.
During DPMS on/off cycle DC6 counter is incremented.
v2: Renamed the subtest name.
v3: Rebased.
v4: Rebased and address review comment.
Signed-off-by: Jyoti Yadav
Signed-off-by: Anshuman Gupta
---
tests/pm_dc.c | 9
Signed-off-by: Anshuman Gupta
---
drivers/acpi/processor_driver.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c
index ee842a2f..9d6aff2 100644
--- a/drivers/acpi/processor_driver.c
+++ b/dr
for ICL.
Cc: martin.pe...@intel.com
Cc: daniel.vet...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/acpi/processor_driver.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c
index 9d6aff2
, only for ICL.
This hacky patch is only for ICL processor and for Core-for-CI branch.
v2: Fixed compilation errors raised by lkp.
commit message improvement.
Cc: martin.pe...@intel.com
Cc: daniel.vet...@intel.com
Signed-off-by: Anshuman Gupta
---
drivers/acpi/processor_driver.c | 18
On Fri, Feb 08, 2019 at 04:49:31PM +0200, Imre Deak wrote:
> On Fri, Feb 01, 2019 at 09:42:59PM +0530, Anshuman Gupta wrote:
> > From: Jyoti Yadav
> >
> > Currently this test validates DC5 upon PSR entry for supported platforms.
> > Added new file for compilatio
On Fri, Feb 08, 2019 at 04:53:18PM +0200, Imre Deak wrote:
> On Fri, Feb 01, 2019 at 09:43:02PM +0530, Anshuman Gupta wrote:
> > From: Jyoti Yadav
> >
> > Added new subtest for DC6 entry during DPMS on/off cycle.
> > During DPMS on/off cycle DC6 counter is incremente
Enabled has_pc8 global for ICL and Gen9.
Added PC8+ residency test for display enabled case as well.
Signed-off-by: Anshuman Gupta
---
tests/pm_rpm.c | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index be296f5..c84f199 100644
Do not assert failure if PC8 state achieved with display enabled.
Signed-off-by: Anshuman Gupta
---
tests/pm_rpm.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/tests/pm_rpm.c b/tests/pm_rpm.c
index c84f199..878b63b 100644
--- a/tests/pm_rpm.c
+++ b/tests/pm_rpm.c
This patch series enable PC8+ residency test, earlier these tests
were only enabled for Haswell and Broadwell.
Anshuman Gupta (2):
tests/pm_rpm: Enable PC8+ residency test for ICL and GEN9.
tests/pm_rpm: Enable modeset-pc8-residency-stress for ICL and GEN9.
tests/pm_rpm.c | 21
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915
() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 43
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 45
eDP panel.
(when system boots with only eDP panel there will not be real
modeset). I observed sometimes hang while early bootup, which
seems side effect of forcing a modeset at bootup. I am working
to fix it.
Tagging this as RFC series, i need feedback, suggestion and ACK
to this new design.
Anshuma
deset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset at bootup to enable and configure
DC3CO exitline.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 2 +
.../drm
drigo Vivi
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 106 ++
.../drm/i915/display/intel_display_power.h| 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 89 insertions(+), 20 deletions(-)
diff --git a/drivers/gp
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
Hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: use frontbuffer flush mechanism. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Ansh
l.
Tested this series on real H/W, DC3CO counter is validated
without any other issue observed.
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable DC3CO state in "DC Off" power
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
deset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset at bootup to enable and configure
DC3CO exitline.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm
() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 43
drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
2 files changed, 45
ned-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 106 ++
.../drm/i915/display/intel_display_power.h| 2 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 89 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i9
Hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: use frontbuffer flush mechanism. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Ansh
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Adding following definition to i915_reg.h
1. DC_STATE_EN register DC3CO bit fields and masks.
2. Transcoder EXITLINE register and its bit fields and mask.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file
Hence dropping it, dc5_idle_thread() checks the valid wakeref before
putting the reference count, which avoids any chances of dropping
a zero wakeref. [Imre (IRC)]
v4: use frontbuffer flush mechanism. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Ansh
ned-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 111 ++
.../drm/i915/display/intel_display_power.h| 3 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
3 files changed, 95 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i9
pipe config state in encoder disable path.
v1: moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 51
deset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset at bootup to enable and configure
DC3CO exitline.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm
Enable dc3co state in enable_dc module param and add dc3co
enable mask to allowed_dc_mask and gen9_dc_mask.
v1: Adding enable_dc=3,4 options to enable DC3CO with DC5 and DC6
independently.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
are most welcome for this new design
series.
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable DC3CO state in "DC Off" power well
drm/i915/tgl: Do modeset to enable and confi
On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
Hi Imre,
Thanks for reviewing the pacthes i will rework the patches.
There are few comments from my side which will help to rework.
> > Add max_dc_state and tgl_set_target
On 2019-09-08 at 20:55:17 +0300, Imre Deak wrote:
Hi Imre ,
Thanks for review, could you please provide your response on below
comments.
> On Sat, Sep 07, 2019 at 10:44:42PM +0530, Anshuman Gupta wrote:
> > DC3CO is useful power state, when DMC detects PSR2 idle frame
> > while
On 2019-09-11 at 11:50:26 +0300, Imre Deak wrote:
> On Tue, Sep 10, 2019 at 03:26:20PM +0530, Anshuman Gupta wrote:
> > On 2019-09-08 at 20:55:17 +0300, Imre Deak wrote:
> > Hi Imre ,
> > Thanks for review, could you please provide your response on below
> > comments.
&g
On 2019-09-11 at 11:21:42 +0300, Imre Deak wrote:
> On Mon, Sep 09, 2019 at 09:49:17PM +0530, Anshuman Gupta wrote:
> > On 2019-09-08 at 19:44:35 +0300, Imre Deak wrote:
> > > On Sat, Sep 07, 2019 at 10:44:39PM +0530, Anshuman Gupta wrote:
> > Hi Imre,
> > Thanks fo
v8 revision is a rework of series, which has fixed the review comments
provided by Imre and Animesh.
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required register and bits
drm/i915/tgl: Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
drm/i915/tgl: Enable DC3CO state in "DC Off&q
instead of allowed_dc_mask
in "DC off" power well callback. [Imre]
Adding "DC off" power well id to older platforms. [Imre]
Removed psr2_deep_sleep flag from tgl_set_target_dc_state. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gu
AMES macro. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 97 +++
.../drm/i915/display/intel_display_power.h| 4 +
.../gpu/drm/i915/display/intel_frontbuffer.c | 1 +
drivers/gp
pipe config state in encoder disable path.
v1: Moved calling of tgl_enable_psr2_transcoder_exitline() to
intel_psr_enable(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Cc: José Roberto de Souza
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 51
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..6bfebab9a441 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915
: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
b
deset as BIOS has already programmed the necessary registers,
therefore it needs to force a modeset to enable and configure
DC3CO exitline.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +
.../drm/i915/di
On 2019-09-23 at 19:42:02 +0300, Imre Deak wrote:
> On Fri, Sep 13, 2019 at 01:53:37PM +0530, Anshuman Gupta wrote:
> > Add dc3co helper functions to enable/disable psr2 deep sleep.
> > Adhere B.Specs by disallow DC3CO state before PSR2 exit.
> > Enable PSR2 exitline event an
On 2019-09-23 at 19:26:56 +0300, Imre Deak wrote:
> On Fri, Sep 13, 2019 at 01:53:36PM +0530, Anshuman Gupta wrote:
> > DC3CO enabling B.Specs sequence requires to enable end configure
> > exit scanlines to TRANS_EXITLINE register, programming this register
> > has to be par
On 2019-09-23 at 19:26:56 +0300, Imre Deak wrote:
> On Fri, Sep 13, 2019 at 01:53:36PM +0530, Anshuman Gupta wrote:
> > DC3CO enabling B.Specs sequence requires to enable end configure
> > exit scanlines to TRANS_EXITLINE register, programming this register
> > has to be par
Nikula
Cc: Imre Deak
Cc: Animesh Manna
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ecebc82f..6bfebab9a441
AMES macro. [Imre]
v6: Inited the busy_frontbuffer_bits, used dc3co_exitline check instead
of TGL and dc3co allowed_dc_mask checks, used delayed_work_pending
with the psr lock and removed the psr2_deep_slp_disabled flag. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by
v9 revision is a rework of series, which has fixed the review comments
provided by Imre and added Animesh's RB on following two patches.
1.Add DC3CO required register and bits
2.Add DC3CO mask to allowed_dc_mask and gen9_dc_mask
Anshuman Gupta (7):
drm/i915/tgl: Add DC3CO required registe
Checking DC3CO state against allowed DC mask, using WARN_ON()
in tgl_set_target_dc_state(). [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 110 --
.../drm/i915/display/intel_display_power
coder pre_enable and post_disable hooks. [Imre]
Computing dc3co_exitline instead of has_dc3co_exitline bool. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_ddi.c | 7 ++
drivers/gpu/drm/i915/display/intel_disp
the patches where they are getting used and used dc3co_exitline
check instead of TGL check. [Imre]
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_psr.c | 8
drivers/gpu/drm/i915/i915_drv.h | 1 +
2 files
Adding DC3CO counter in i915_dmc_info debugfs will be
useful for DC3CO validation.
DMC firmware uses DMC_DEBUG3 register as DC3CO counter
register on TGL, as per B.Specs DMC_DEBUG3 is general
purpose register.
Cc: Jani Nikula
Cc: Imre Deak
Cc: Animesh Manna
Signed-off-by: Anshuman Gupta
: Animesh Manna
Reviewed-by: Animesh Manna
Signed-off-by: Anshuman Gupta
---
.../drm/i915/display/intel_display_power.c| 29 +++
drivers/gpu/drm/i915/i915_params.c| 3 +-
2 files changed, 25 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
cause silicons at local BA setup
are not entering to PC2 itself.
Planning a separate series for a subtest to validate pc8 with multiple pipes
and all planes enabled to create maximum memory bandwidth scenario.
Anshuman Gupta (2):
tests/i915/i915_pm_rpm: Enable PC8+ residency test for ICL
tests
Enabled has_pc8 global for ICL and Gen9.
Added PC8+ residency test for display enabled case as well.
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_rpm.c | 75 +++-
1 file changed, 68 insertions(+), 7 deletions(-)
diff --git a/tests/i915
Introduced pc8_needs_screen_off flag in order to differentiate
between HASWELL/BROADWEEL and AT_LEAST_GEN9. GEN9 onwards
PC8+ residency does't require display to be turned on.
Signed-off-by: Anshuman Gupta
---
tests/i915/i915_pm_rpm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
This patch series adds new tests to validate Display C states.
DC states like DC5 and DC6 are validated during PSR entry/exit
and during DPMS on/off cycle.
Sending new revision of patch series after addressing review comments and
other relevant changes.
1. Changing the name of test from pm_dc to
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