fault on all dGPU")'
It will reduce the DG2 Card power consumption to ~0 Watt
for s2idle power KPI.
v2:
- Added "Cc: sta...@vger.kernel.org".
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8755
Cc: sta...@vger.kernel.org
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
fault on all dGPU")'
It will reduce the DG2 Card power consumption to ~0 Watt
for s2idle power KPI.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/8755
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c | 33 --
1 fi
DGFX uses similar PCODE MBOX interface as IGFX but
uses distinct COMMAND and PARAM set of bit fields.
Adding those headers Accordingly.
Cc: Rodrigo Vivi
Signed-off-by: Ashutosh Dixit
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_reg.h | 3 +++
1 file changed, 3 insertions
Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm
invokes runtime_idle
callback when runtime usages count becomes zero. That requires
to use pm_runtime_put instead of pm_runtime_put_autosuspend.
Cc: Rodrigo Vivi
Cc: Chris Wilson
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c | 26 +
drivers/gpu
Add DG2 Motherboard Down Config check support.
BSpec: 44477
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 9 +
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915
VRSR.
BSpec: 53440
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 36 +++
drivers/gpu/drm/i915/display/intel_opregion.h | 6
2 files changed, 42 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
is stable.
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers
This series add DG2 D3Cold VRAM_SR support.
TODO: GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (7):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: DG2 MBD config
drm/i915/dgfx: Add has_lmem_sr
will evict
lmem objects without VRSR.
VRSR feature requires Host BIOS support, VRSR will be enable/disable
by HOST BIOS using ACPI OpRegion.
Adding OpRegion VRSR support in order to enable/disable
VRSR on discrete cards.
BSpec: 53440
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman
This series add DG2 D3Cold VRAM_SR support.
TODO: GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (7):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: DG2 MBD config
drm/i915/dgfx: Add has_lmem_sr
From: Tvrtko Ursulin
Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.
v2:
- Use forward decalaration instead of heder file. [Jani]
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Anshuman Gupta
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c | 11 ++
drivers/gpu/drm/i915/i915_params.c | 4 ++
drivers/gpu/drm/i915/i915_params.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 50 +
drivers/gpu/drm/i915/intel_pm.h | 1
This series add DG2 D3Cold VRAM_SR support.
TODO: GT and GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (8):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: Add DG2_NB_MBD subplatform
drm/i915/dg2
ration. [Jani]
BSpec: 53440
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 78 ++-
drivers/gpu/drm/i915/display/intel_opregion.h | 17
2 files changed, 94 insertions(+), 1 deletion(-)
diff --git a/drivers/g
vram_sr.
v2:
- Removed IS_DG1() cond from intel_opregion_dg1_mbd_config. [Jani]
- Moved intel_opregion_vram_sr_required() to prev patch.
BSpec: 53440
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 21 +++
1
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
v2:
- Adding only required MBD subplatform. [Jani, Matt]
Cc: Matt Roper
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 2
Cc: Chris Wilson
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c | 26 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +--
2 files changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gp
Add DG2 Motherboard Down Config check condition
to intel_opregion_vram_sr_required().
v2:
- Use MBD Subplatform to check DG2 MBD. [Jani]
BSpec: 44477
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
1 file changed, 2 insertions(+)
diff
is stable.
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers
Redundant !HAS_LMEM_SR(i915). [Jani]
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h| 2 ++
drivers/gpu/drm/i915/i915_reg.h| 4 +++
drivers/gpu/drm/i915/intel_pcode.h | 1 +
drivers/gpu/drm/i915
Possible regressions ####
Below are unrelated failures on GLK, not cause by this patch.
Pushed to drm-intel-next, thanks for Ack and Review.
Br,
Anshuman Gupta.
>
> * igt@kms_concurrent@pipe-b:
> - shard-glk: NOTRUN -> [TIMEOUT][1]
>[1]:
> https://intel-gfx-ci.01.o
")
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c | 34 +-
1 file changed, 15 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_driver.c
b/drivers/gpu/drm/i915/i915_driver.c
index d26dcca7e654..86f9f0be7
i915 must disable Render DOP clock gating globally.
v2:
- Addressed cosmetic review comments.
Bspec: 52621
Cc: Matt Roper
Cc: Badal Nilawar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
2 files
i915 must disable Render DOP clock gating globally.
B.Spec: 52621
Cc: Matt Roper
Cc: Badal Nilawar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 +
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/drivers
From: Tvrtko Ursulin
Store a pointer to respective local memory region in intel_gt so it can be
used when memory local to a GT needs to be allocated.
Cc: Andi Shyti
Signed-off-by: Tvrtko Ursulin
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/intel_gt.c | 1 +
drivers/gpu
-vram_sr
sequence.
FIXME: Eviction of lmem objects in case of D3Cold off is wip.
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c | 27 ---
drivers/gpu/drm/i915/i915_params.c | 4
drivers/gpu/drm/i915/i915_params.h | 3 ++-
3
invokes runtime_idle
callback when runtime usages count becomes zero. That requires
to use pm_runtime_put instead of pm_runtime_put_autosuspend.
TODO: GuC interface state save/restore.
Cc: Rodrigo Vivi
Cc: Chris Wilson
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_driver.c
Setup VRAM Self Refresh with D3COLD state.
VRAM Self Refresh will retain the context of VRAM, driver
need to save any corresponding hardware state that needs
to be restore on D3COLD exit, example PCI state.
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm
VRSR.
BSpec: 53440
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 43 +++
drivers/gpu/drm/i915/display/intel_opregion.h | 6 +++
2 files changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/display
DG2 NB SKU need to distinguish between MBD and AIC to probe
the VRAM Self Refresh feature support. Adding those sub platform
accordingly.
Cc: Matt Roper
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 3 +++
drivers/gpu/drm/i915/intel_device_info.c | 21
This series add DG2 D3Cold VRAM_SR support.
TODO: GuC Interface state save/restore on VRAM_SR entry/exit.
Anshuman Gupta (8):
drm/i915/dgfx: OpRegion VRAM Self Refresh Support
drm/i915/dg1: OpRegion PCON DG1 MBD config support
drm/i915/dg2: Add DG2_NB_MBD subplatform
drm/i915/dg2: DG2
will evict
lmem objects without VRSR.
VRSR feature requires Host BIOS support, VRSR will be enable/disable
by HOST BIOS using ACPI OpRegion.
Adding OpRegion VRSR support in order to enable/disable
VRSR on discrete cards.
BSpec: 53440
Cc: Jani Nikula
Cc: Rodrigo Vivi
Signed-off-by: Anshuman
Add DG2 Motherboard Down Config check support.
v2:
- Don't use pciid to check DG2 MBD. [Jani]
BSpec: 44477
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 2 ++
drivers/gpu/drm/i915/i915_drv.h | 9 +
2 files changed, 11
is stable.
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_pci.c | 2 ++
drivers/gpu/drm/i915/intel_device_info.h | 1 +
3 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers
. Disabling/Enabling d3cold at
gfx root port in probe/remove phase is sufficient.
Fixes: 1a085e23411d ("drm/i915: Disable D3Cold in s2idle and runtime pm")
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
Reviewed-by: Badal Nilawar
---
drivers/gpu/drm/i915/i915_dri
on DG1 as it
relies on mercy of i915 driven runtime resume.
Let's not break using mmap() for lmem object on DG1.
Using pci_d3cold_disable(i915) accordingly to disable D3 for
upstream bridge.
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6331
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
/uc/intel_guc_slpc.c
> @@ -152,8 +152,8 @@ static int slpc_query_task_state(struct intel_guc_slpc
> *slpc)
>
> ret = guc_action_slpc_query(guc, offset);
> if (unlikely(ret))
As commit logs describe, this code patch can hit, when we run error injection
test.
Do we need unlike
Adding intel_opregion_init() wrapper function, which encapsulates
intel_opregion_setup() and will be used for other opregion specific
initialization.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 12 +++-
drivers/gpu/drm/i915/display/intel_opregion.h
addressed Abstraction Level related review comment from Jani.
Anshuman Gupta (6):
drm/i915/opregion: Add intel_opregion_init() wrapper
drm/i915/opregion: Abstract opregion function
drm/i915/opregion: Add dgfx opregion func
drm/i915/opregion: Cond dgfx opregion func registration
drm/i915/d
l Nilawar
Cc: Uma Shankar
Signed-off-by: Manasi Navare
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 177 +-
drivers/gpu/drm/i915/display/intel_opregion.h | 3 +
2 files changed, 133 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu
(), and added necessary
credit to Manasi.
v4:
- Fix free_{opregion, rvda} abstraction level. [Jani]
PCI Firmware Spec: ID:12886
https://pcisig.com/specifications
Cc: Jani Nikula
Cc: Rodrigo Vivi
Cc: Uma Shankar
Cc: Badal Nilawar
Signed-off-by: Manasi Navare
Signed-off-by: Anshuman Gupta
Cc: Rodrigo Vivi
Cc: Badal Nilawar
Signed-off-by: Manasi Navare
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c
b/drivers/gpu/
Adding DGFX opregion dummy functions.
These will be setup later to support dgfx opregion.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 34 +--
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
condition for IS_DGFX() and HAS_DISPLAY(). [Jani]
Cc: Badal Nilawar
Cc: Jani Nikula
Cc: Uma Shankar
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/display/intel_opregion.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display
RPM suspend/resume also supported on gfx platforms which doesn't have
kms support and even on platforms without any connected display panel.
There is no good reason to log rpm suspend/resume debug message with
drm_dbg_kms() therefore changing it to drm_dbg().
Signed-off-by: Anshuman Gupta
i915_gem_object_pin_map will be handled in
different series.
Anshuman Gupta (1):
drm/i915/dgfx: Release mmap on rpm suspend
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 48 ---
drivers/gpu/drm/i915/gt/intel_gt.c| 2
mem. [Matt Auld]
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6331
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
.../gpu/drm/i915/gem/i915_gem_object_types.h | 3 +-
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 48 ---
drivers/gpu/drm/i915
Runtime pm is not really per GT, therefore it make sense to
move lmem_userfault_list, lmem_userfault_lock and
userfault_wakeref from intel_gt to intel_runtime_pm structure,
which is embedded to i915.
No functional change.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem
} from intel_gt. [Matt Auld]
Fixes: ad74457a6b5a ("drm/i915/dgfx: Release mmap on rpm suspend")
Suggested-by: Matthew Auld
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 19 +---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 38
} from intel_gt. [Matt Auld]
Fixes: ad74457a6b5a ("drm/i915/dgfx: Release mmap on rpm suspend")
Suggested-by: Matthew Auld
Signed-off-by: Anshuman Gupta
Reviewed-by: Matthew Auld
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 19 +---
drivers/gpu/drm/i915/gem/i915
v3 series rev fixes the nit review comment.
Anshuman Gupta (2):
drm/i915: Encapsulate lmem rpm stuff in intel_runtime_pm
drm/i915/dgfx: Grab wakeref at i915_ttm_unmap_virtual
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 21 +---
drivers/gpu/drm/i915/gem/i915_gem_pm.c | 2
Runtime pm is not really per GT, therefore it make sense to
move lmem_userfault_list, lmem_userfault_lock and
userfault_wakeref from intel_gt to intel_runtime_pm structure,
which is embedded to i915.
No functional change.
v2:
- Fixes the code comment nit. [Matt Auld]
Signed-off-by: Anshuman
While reading the engine timestamps there can be uncontrollable
concurrent mmio access via other i915 child drivers and by GuC,
which may cause mmio latency to read the engine timestamps,
Account such latency to calculate time to read engine timestamp.
Signed-off-by: Anshuman Gupta
---
drivers
l test robot generated warning.
PCIe Specs 5.3.1.4.1
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6331
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 21 +
drivers/gpu/drm/i915/gem/i915_gem_mman.h
as Unexpected Completions.
Therefore when gfx endpoint function is in d3 state, all pcie iomem
transaction requires to transition the pcie function in D0 state.
Implementation of handling i915_gem_object_pin_map will be handled in
different series.
Anshuman Gupta (2):
drm/i915: Refactor
Refactor userfault_wakeref to re-use for discrete lmem mmap mapping
as well, as on discrete GTT mmap are not supported. Moving
userfault_wakeref from ggtt to gt structure.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem
and DG2.
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 77e7df21f539..28f38f1cc5cc 100644
--- a/drivers/gpu/drm/i915
a smaller FIXME code comment for both DG1/DG2.
Cc: Matthew Auld
Cc: Rodrigo Vivi
Reviewed-by: Rodrigo Vivi
Reviewed-by: Andi Shyti
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/i915_pci.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915
:
With respect to i915_gem_object_pin_map(), every caller
has to grab a wakeref if gem object lies in lmem.
Till we fix all issues related to runtime PM, we need
to keep runtime PM disable on both DG1 and DG2.
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm
Cc: Rodrigo Vivi
Cc: Andi Shyti
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_object.c | 2 ++
drivers/gpu/drm/i915/gem/i915_gem_object.h | 5 +
drivers/gpu/drm/i915/gem/i915_gem_object_types.h | 14 ++
drivers/gpu/drm/i915/gem/i915_gem_pages.c
of i915_gem_onject_pin_map() does not need to grab
the wakeref. We can embedded the wakeref inside the gem object itself.
Requesting community to provide the feedback on this proposal.
Anshuman Gupta (1):
drm/i915/dgfx: Handling of pin_map against rpm
drivers/gpu/drm/i915/gem/i915_gem_object.c | 2
Adding support in drpc show debugfs to print the GT RPM Unit RC6
residency. This GTC6_RESIDENCY_{LSB, MSB} will only increment when
GT will be RC6. Therefore these register will get reset at RC6
exit and will start incrementing on next RC6 entry.
BSpec: 64977
Signed-off-by: Anshuman Gupta
uction patch. [Matt Auld]
- Use intel_wakeref_auto to delay runtime PM. [Matt Auld]
PCIe Specs 5.3.1.4.1
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/6331
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c
Refactor userfault_wakeref to re-use for discrete lmem mmap mapping
as well, as on discrete GTT mmap are not supported. Moving
userfault_wakeref from ggtt to gt structure.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu/drm/i915/gem
as Unexpected Completions.
Therefore when gfx endpoint function is in d3 state, all pcie iomem
transaction requires to transition the pcie function in D0 state.
Implementation of handling i915_gem_object_pin_map will be handled in
different series.
Anshuman Gupta (2):
drm/i915: Refactor
Refactor userfault_wakeref to re-use for discrete lmem mmap mapping
as well, as on discrete GTT mmap are not supported. Moving
userfault_wakeref from ggtt to gt structure.
Signed-off-by: Anshuman Gupta
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 2 +-
drivers/gpu
as Unexpected Completions.
Therefore when gfx endpoint function is in d3 state, all pcie iomem
transaction requires to transition the pcie function in D0 state.
Implementation of handling i915_gem_object_pin_map will be handled in
different series.
Anshuman Gupta (2):
drm/i915: Refactor
331
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
Reviewed-by: Andi Shyti
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 21 +++
drivers/gpu/drm/i915/gem/i915_gem_mman.h | 1 +
drivers/gpu/drm/i915/gem/i915_gem_object.c| 2 +-
.../gpu/drm/i9
fx: Release mmap on rpm suspend")
Suggested-by: Matthew Auld
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 19 +---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 39
drivers/gpu/drm/i915/gt/intel_gt.c | 11 ++-
drivers
y: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 6ed5786bcd29..410a5cb58a61 100644
--- a/d
(). [Rodrigo]
Fixes: b908be543e44 ("drm/i915: support creating LMEM objects")
Suggested-by: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ru
solution 1 which effectively
disable the runtime PM.
Caveat with solution 1 that, it doesn't address the case when user
directly maps PCI Bar resource i.e. below mentioned resource.
"/sys/bus/pci/devices/\:03\:00.0/resource2"
Anshuman Gupta (1):
drm/i915/dgfx: Avoid parent bridge r
.
This will make sure that user can read valid data from lmem,
while DGFX Card graphics PCI func is in D3 state.
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_mman.c | 11
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 8 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 35
as Unexpected Completions.
Therefore when gfx endpoint function is in d3 state, all pcie iomem
transaction requires to transition the pcie function in D0 state.
RFC proposal to get community feedback to handle the lmem
mmap memory mappings with runtime suspend.
Anshuman Gupta (2):
drm/i915/dgfx
Release all mmap mapping for all lmem objects which are associated
with userfault such that, while pcie function in D3hot, any access
to memory mappings will raise a userfault.
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 4
Runtime resume the dgpu(when gem object lies in lmem).
This will transition the dgpu graphics function to D0
state if it was in D3 in order to access the mmap memory
mappings.
Cc: Matthew Auld
Cc: Rodrigo Vivi
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 25
Cold Reset IGT Test.
v2:
Address some review comments from Kamil and Badal.
Anshuman Gupta (3):
lib/igt_pm: Refactor get firmware_node fd
test/device_reset: Refactor initiate_device_reset
tests/device_reset: Add cold reset IGT test
lib/igt_pm.c | 76
lib
]
- use igt_assert() when failed to open 'real_power_state' on error
other then ENONET.
Signed-off-by: Anshuman Gupta
---
lib/igt_pm.c | 36 +---
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git a/lib/igt_pm.c b/lib/igt_pm.c
index 1e6e9ed3f..4f0cfbdd1
Added a reset type enum to support multiple types
of reset like WARM, COLD and FLR reset.
No functional change.
v2:
- Removed WARM_RESET enum as not used yet. [Badal]
Signed-off-by: Anshuman Gupta
---
tests/device_reset.c | 20 ++--
1 file changed, 14 insertions(+), 6
Add cold-reset IGT subtest, IGT subtest will use
/sys/bus/pci/slots/$SUN/power sysfs in order to
initiate a cold reset sequence. $SUN value will be
retrieved from PCIe device ACPI firmware node.
v2:
- %s/igt_require(fd > 0)/igt_assert(errno >0)
Signed-off-by: Anshuman Gupta
Reviewed-by:
engine timestamp
such that selftest can validate the timestamp and ktime pair.
Cc: Chris Wilson
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
Use ktime_get() after accessing the mmio or any driver resource,
while using wall time for various calculation that depends on
the inserted delay in order to account any mmio and resource
access latency.
Cc: Chris Wilson
Signed-off-by: Anshuman Gupta
---
drivers/gpu/drm/i915/gt/selftest_rps.c
Few selftest fixes to gt_pm and rps tests.
Anshuman Gupta (2):
drm/i915/selftest: Fix engine timestamp and ktime disparity
drm/i915/selftest: Fix ktime_get() and h/w access order
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 10 +-
2
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