[Intel-gfx] [PATCH 3/5] drm/i915/display: Drop duplicated code in intel_dp_set_infoframes()

No functional changes in here. Cc: Matt Atwood Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dp.c | 17 ++--- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display

[Intel-gfx] [PATCH 4/5] drm/i915/display: Drop dead code from hsw_read_infoframe()

HSW_TVIDEO_DIP_CTL is read but not used. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_hdmi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c index

[Intel-gfx] [PATCH 1/2] drm: Rename DP_PSR_SELECTIVE_UPDATE to better mach eDP spec

drigo Vivi Cc: Jani Nikula Cc: Gwan-gyeong Mun Signed-off-by: José Roberto de Souza --- include/drm/drm_dp_helper.h | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h index 1e85c2021f2f..d6f6a084a190 10

[Intel-gfx] [PATCH 2/2] drm/i915/display/xelpd: Do not program EDP_Y_COORDINATE_ENABLE

EDP_Y_COORDINATE_ENABLE became a reserved register in display 13. EDP_Y_COORDINATE_VALID have the same fate as EDP_Y_COORDINATE_ENABLE but as we don't need it, removing the macro definition of it. BSpec: 50422 Cc: Gwan-gyeong Mun Cc: Anusha Srivatsa Signed-off-by: José Roberto de

[Intel-gfx] [PATCH] drm/i915/display/tgl+: Add new sequence step for MST + FEC

For DP 1.4 sinks + MST + FEC it is required to prevent a FEC stall signaling. BSpec: 49190 BSpec: 54128 Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/display/intel_dp_mst.c | 28 + drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 29

[Intel-gfx] [PATCH v3 2/4] drm/i915: Refactor PSR status debugfs

to parse debugfs for IGT tests. v2: Printing sink PSR version with only 2 hex digits as it is a byte Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Suggested-by: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Acked-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/

[Intel-gfx] [PATCH v3 4/4] drm/i915/debugfs: Print PSR selective update status register values

(Dhinakaran) Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index

[Intel-gfx] [PATCH v3 1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks

switch/case that intel_psr2_enabled() already had to handle this(DK) Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a

[Intel-gfx] [PATCH v3 3/4] drm/i915: Add PSR2 selective update status registers and bits definitions

: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 44958d994bfa..f9712d05314b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH 1/4] drm/i915/vbt: Add 'tp4' to varibles holding TP2/3/4 PSR wakeup time

Recent update in spec made the field holding the TP2 and TP3 wakeup time for PSR also hold the TP4, so lets rename the variables to reflect that. BSpec: 20131 Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 4/4] drm/i915/psr: Add HBR3 support

If the sink and source supports HBR3, TP4 should be used as link training pattern. For PSR2 there is no register to set and enable TP4 but according to eDP spec TP3 is still a training pattern acceptable for HBR3 panels. Cc: Manasi Navare Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de

[Intel-gfx] [PATCH 2/4] drm/i915/psr: Store VBT TP wakeup times into a enum

Newer VBTs and the PSR registers uses a enum to set the TPs wakeup time, so lets use this format to store wakeup times and avoid conversions every time that PSR is activated. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 12 +- drivers

[Intel-gfx] [PATCH 3/4] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3/4 wakeup time

A new field with the training pattern(TP) wakeup time for PSR2 was added to VBT, so lets use it when available otherwise it will fallback to PSR1 wakeup time. BSpec: 20131 Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 8

[Intel-gfx] [PATCH v4 1/4] drm/i915/psr: Allow PSR2 to be enabled when debugfs asks

switch/case that intel_psr2_enabled() already had to handle this(DK) Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a

[Intel-gfx] [PATCH v4 3/4] drm/i915: Add PSR2 selective update status registers and bits definitions

: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 9 + 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 9a1340cfda6c..a78789cc0e8f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h

[Intel-gfx] [PATCH v4 4/4] drm/i915/debugfs: Print PSR selective update status register values

(Dhinakaran) Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 23 +++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm

[Intel-gfx] [PATCH v4 2/4] drm/i915: Refactor PSR status debugfs

to parse debugfs for IGT tests. v2: Printing sink PSR version with only 2 hex digits as it is a byte Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Suggested-by: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Acked-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/

[Intel-gfx] [PATCH] drm/i915/icl: Delay hotplug sequence for TC ports

should be extended to TBT ports too. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_ddi.c | 4 + drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_hotplug.c | 108 +++ 4 files

[Intel-gfx] [PATCH 3/4] drm/psr: Do not enable PSR when a interlaced mode set for all gens

This interlaced restriction applies to all gens, not only to Haswell. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b

[Intel-gfx] [PATCH 1/4] drm/i915/psr: Remove PSR2 FIXME

Now we are only checking sink capabilities when probing PSR DPCD register and then dynamically checking in intel_psr2_config_valid() to make sure the current modeset and features enables are compatible with PSR2. So this FIXME can be dropped. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto

[Intel-gfx] [PATCH 2/4] drm/i915/psr: Initialize PSR mutex even when sink is not reliable

Even when driver is reload and hits this scenario the PSR mutex should be initialized, otherwise reading PSR debugfs status will execute mutex_lock() over a mutex that was not initialized. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 1

[Intel-gfx] [PATCH 4/4] drm/i915/psr: Print why PSR or PSR2 was not enabled in debugfs

PSR2 reason even if PSR1 is enabled as PSR2 have some additional requirements. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 2 ++ drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c| 13

[Intel-gfx] [PATCH] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug

. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341 Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +-- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_ddi.c| 2

[Intel-gfx] [PATCH v2] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug

: Handling missing case: disabled to PSR1 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341 Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- Should I add IGT tests to test every state switch combination? drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug

: Handling missing case: disabled to PSR1 v3: Not duplicating the whole atomic state(Maarten) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108341 Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c

[Intel-gfx] [PATCH 5/7] drm/i915/bdw+: Move misc display IRQ handling to it own function

Just moving it to reduce the tabs and avoid break code lines. No behavior changes intended here. Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 63 +++-- 1 file changed, 36 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/7] drm/i915: Remove unused VLV/CHV PSR registers

PSR support for VLV and CHV was dropped in commit ce3508fd2a77 ("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep this registers around. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_

[Intel-gfx] [PATCH 1/7] drm/i915/psr: Update PSR2 SU corruption workaround comment

Turn out it is not a DMC bug it is actually a HW one, so this workaround will be needed for current gens, lets update the comment and remove the FIXME. BSpec: 7723 Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 6 ++ 1

[Intel-gfx] [PATCH 6/7] drm/i915/psr: Remove partial PSR support on multiple transcoders

PSR is only supported in eDP transcoder and there is only one instance of it, so lets drop all of this code. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 17 +--- drivers/gpu/drm/i915/intel_psr.c | 147

[Intel-gfx] [PATCH 7/7] drm/i915: Make PSR registers relative to transcoders

n Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 5 ++- drivers/gpu/drm/i915/i915_reg.h | 59 - drivers/gpu/drm/i915/intel_psr.c

[Intel-gfx] [PATCH 3/7] drm/i915/psr: Initialize PSR mutex even when sink is not reliable

Even when driver is reloaded and hits this scenario the PSR mutex should be initialized, otherwise reading PSR debugfs status will execute mutex_lock() over a mutex that was not initialized. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 4/7] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs

This interlaced restriction applies to all gens, not only to Haswell. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b

[Intel-gfx] [PATCH 1/4] drm/i915/psr: Update PSR2 SU corruption workaround comment

Turn out it is not a DMC bug it is actually a HW one, so this workaround will be needed for current gens, lets update the comment and remove the FIXME. BSpec: 7723 Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/4] drm/i915: Remove unused VLV/CHV PSR registers

PSR support for VLV and CHV was dropped in commit ce3508fd2a77 ("drm/i915/psr: Nuke PSR support for VLV and CHV") so no need to keep this registers around. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gp

[Intel-gfx] [PATCH 4/4] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs

This interlaced mode restriction applies to all gens, not only to Haswell. Also while at it updating the debug message to. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 3/4] drm/i915/psr: Initialize PSR mutex even when sink is not reliable

Even when driver is reloaded and hits this scenario the PSR mutex should be initialized, otherwise reading PSR debugfs status will execute mutex_lock() over a mutex that was not initialized. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v2 2/3] drm/i915/psr: Remove partial PSR support on multiple transcoders

Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 17 +--- drivers/gpu/drm/i915/intel_psr.c | 147 --- 2 files changed, 42 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index

[Intel-gfx] [PATCH v2 1/3] drm/i915/bdw+: Move misc display IRQ handling to it own function

Just moving it to reduce the tabs and avoid break code lines. No behavior changes intended here. v2: - Reading misc display IRQ outside of gen8_de_misc_irq_handler() as other irq handlers (Dhinakaran) Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v2 3/3] drm/i915: Make PSR registers relative to transcoders

n Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 5 ++- drivers/gpu/drm/i915/i915_reg.h | 59 - drivers/gpu/drm/i915/intel_psr.c

[Intel-gfx] [PATCH v3 4/5] drm/i915: Make PSR registers relative to transcoders

n Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 5 +-- drivers/gpu/drm/i915/i915_reg.h | 52 - drivers/gpu/drm/i915/intel_psr.c

[Intel-gfx] [PATCH v3 2/5] drm/i915/psr: Remove partial PSR support on multiple transcoders

Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 17 +--- drivers/gpu/drm/i915/intel_psr.c | 147 --- 2 files changed, 42 insertions(+), 122 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu

[Intel-gfx] [PATCH v3 5/5] drm/i915: Add transcoder parameter to PSR registers macros

Lets make PSR register macros explicit about what transcoder is used to calculate the register offset. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 18 ++ drivers/gpu/drm/i915/i915_reg.h | 26

[Intel-gfx] [PATCH v3 1/5] drm/i915/bdw+: Move misc display IRQ handling to it own function

Just moving it to reduce the tabs and avoid break code lines. No behavior changes intended here. v2: - Reading misc display IRQ outside of gen8_de_misc_irq_handler() as other irq handlers (Dhinakaran) Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v3 3/5] drm/i915: Add _TRANS2()

-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e2803b120b6d..36420af2cd6f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu

[Intel-gfx] [PATCH v4 3/4] drm/i915: Make PSR registers relative to transcoders

a Cc: Ville Syrjälä Cc: Zhi Wang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i915_drv.h | 5 +-- drivers/gpu/drm/i915/i915_reg.h | 48 - drivers/gpu/drm/i915/intel_psr.c| 11 +-- 4 files change

[Intel-gfx] [PATCH v4 4/4] drm/i915: Add transcoder parameter to PSR registers macros

Lets make PSR register macros explicit about what transcoder is used to calculate the register offset. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 18 ++ drivers/gpu/drm/i915/i915_reg.h | 24

[Intel-gfx] [PATCH v4 1/4] drm/i915/bdw+: Move misc display IRQ handling to it own function

Just moving it to reduce the tabs and avoid break code lines. No behavior changes intended here. v2: - Reading misc display IRQ outside of gen8_de_misc_irq_handler() as other irq handlers (Dhinakaran) Cc: Dhinakaran Pandiyan Reviewed-by: Rodrigo Vivi Signed-off-by: José Roberto de Souza

[Intel-gfx] [PATCH v4 2/4] drm/i915: Add _TRANS2()

-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b74824f0b5b1..9ef306b79e0d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu

[Intel-gfx] [PATCH v5 3/3] drm/i915: Make PSR registers relative to transcoders

akaran) - Squashed with the patch that added the tran parameter to the macros (Dhinakaran) Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Cc: Zhi Wang Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/gvt/handlers.c | 1 - drivers/gpu/drm/i915/i

[Intel-gfx] [PATCH v5 1/3] drm/i915/bdw+: Move misc display IRQ handling to it own function

-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_irq.c | 45 ++--- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b92cfd69134b..a1299f10ed49 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH v5 2/3] drm/i915: Add _TRANS2()

: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b74824f0b5b1..31163415479d

[Intel-gfx] [PATCH v4] drm/i915/psr: Execute the default PSR code path when setting i915_edp_psr_debug

-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 14 +-- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_ddi.c| 2 +- drivers/gpu/drm/i915/intel_drv.h| 6 +- drivers/gpu/drm/i915/intel_psr.c| 182 5 files

[Intel-gfx] [PATCH 1/6] drm/i915: Compute has_drrs after compute has_psr

ff-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_dp.c | 49 ++--- 1 file changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index cf709835fb9a..9f979ac0b692 100644 --- a/drivers/gpu/drm

[Intel-gfx] [PATCH 3/6] drm/i915/drrs: Refactor intel_dp_set_drrs_state()

s already checked or guaranteed in the callers Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_debugfs.c | 9 ++- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_dp.c | 88 +++---

[Intel-gfx] [PATCH 4/6] drm/i915/psr: Remove PSR2 FIXME

Now we are checking sink capabilities when probing PSR DPCD register and then dynamically checking in if new state is compatible with PSR in, so this FIXME can be dropped. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 5 - 1 file

[Intel-gfx] [PATCH 5/6] drm/i915/psr: Initialize PSR mutex even when sink is not reliable

Even when driver is reload and hits this scenario the PSR mutex should be initialized, otherwise reading PSR debugfs status will execute mutex_lock() over a mutex that was not initialized. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 1

[Intel-gfx] [PATCH 6/6] drm/i915/psr: Do not enable PSR in interlaced mode for all GENs

This interlaced restriction applies to all gens, not only to Haswell. Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b

[Intel-gfx] [PATCH 2/6] drm/i915/drrs: Disable DRRS when needed in fastsets

://bugs.freedesktop.org/show_bug.cgi?id=109263 Cc: Hans de Goede Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- drivers/gpu/drm/i915/intel_dp.c | 63 drivers/gpu/drm/i915/intel_drv.h | 2 + 3 files

[Intel-gfx] [PATCH 1/2] drm/i915/hotplug: Move iteration over connectors to other function

The next patch will need to a second iteration over connectors so moving it to a function, no behavior changes intended here. While at it moving intel_connector and intel_encoder to inside of the block that actually uses it. Cc: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu

[Intel-gfx] [PATCH 2/2] drm/i915/icl: Probe again type-c connectors that failed

every type-c connector that failed in the initial probe. Cc: Imre Deak Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_dp.c | 3 +++ drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_hotplug.c | 39 +++- 3 files changed, 37

[Intel-gfx] [PATCH 3/4] drm/i915/psr: Remove PSR2 FIXME

Now we are checking sink capabilities when probing PSR DPCD register and then dynamically checking in if new state is compatible with PSR in, so this FIXME can be dropped. Reviewed-by: Dhinakaran Pandiyan Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH 1/4] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset

expected behavior or not but in the mean time this fix the issue. Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b

[Intel-gfx] [PATCH 4/4] drm/i915: Enable PSR2 by default

-by: José Roberto de Souza --- We can hold this patch a little longer, I'm mainly sending it to show that 'drm/i915: Disable PSR2 while getting pipe CRC' fixed the CRC tests when PSR2 is enabled. drivers/gpu/drm/i915/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --gi

[Intel-gfx] [PATCH 2/4] drm/i915: Disable PSR2 while getting pipe CRC

-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 1 + drivers/gpu/drm/i915/intel_pipe_crc.c | 10 ++ drivers/gpu/drm/i915/intel_psr.c | 23 +++ 4 files changed, 35 insertions(+) diff --git a

[Intel-gfx] [PATCH] drm/i915: Call MG_DP_MODE() macro with the right parameters order

rup Cc: Manasi navare Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index ea83071a22c4..1355be8dec3b 10064

[Intel-gfx] [PATCH 2/2] drm/i915/icl: Probe again type-c connectors that failed

type-c dongles to boot. Cc: Ville Syrjälä Cc: Imre Deak Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 13 + 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index

[Intel-gfx] [PATCH 1/2] drm/i915: Add support for retrying hotplug

From: Imre Deak There is some scenarios that we are aware that sink probe can fail, so lets add the infrastructure to let hotplug() hook to request another probe after some time. Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza Signed-off-by: Jani Nikula Signed-off-by: Imre Deak

[Intel-gfx] [PATCH 1/2] drm/i915: Fix atomic state leak when resetting HDMI link

Atomic state needs to be put even if the commit was successful. Fixes: dba14b27dd3c ("drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD") Cc: Ville Syrjälä Cc: Lyude Paul Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 7 +-- 1 file

[Intel-gfx] [PATCH 2/2] drm/i915: Don't manually add connectors and planes state

drm_atomic_commit() call chain already takes care of adding connectors and planes, so lets no add then manually if not changing their states. Cc: Ville Syrjälä Cc: Lyude Paul Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 8 1 file changed, 8 deletions

[Intel-gfx] [PATCH v3 2/6] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset

expected behavior or not but in the mean time this fix the issue. Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers

[Intel-gfx] [PATCH v3 5/6] drm/i915: Disable PSR2 while getting pipe CRC

lculations. Cc: Dhinakaran Pandiyan Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + drivers/gpu/drm/i915/intel_psr.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_p

[Intel-gfx] [PATCH v3 6/6] drm/i915: Enable PSR2 by default

-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index f7730b8b2ec0..f168f92912eb 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 3/6] drm/i915: Compute and commit color features in fastsets

. Cc: Ville Syrjälä Cc: Maarten Lankhorst Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 7c5e84ef5171

[Intel-gfx] [PATCH v3 1/6] drm/i915/psr: Remove PSR2 FIXME

Now we are checking sink capabilities when probing PSR DPCD register and then dynamically checking in if new state is compatible with PSR in, so this FIXME can be dropped. Reviewed-by: Dhinakaran Pandiyan Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v3 4/6] drm/i915/crc: Make IPS workaround generic

: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_display.c | 10 +-- drivers/gpu/drm/i915/intel_drv.h | 3 +- drivers/gpu/drm/i915/intel_pipe_crc.c | 42 +-- 3 files changed, 24 insertions(+), 31 deletions(-) diff --git a/drivers

[Intel-gfx] [PATCH 3/3] drm/i915: Forcing a modeset when resetting HDMI link

: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index c22ddde2dfc1..d329f0c206ec 100644 --- a/drivers/gpu/drm/i915

[Intel-gfx] [PATCH 2/3] drm/i915: Don't manually add connectors and planes state

ectors() drm_atomic_add_affected_planes() Reviewed-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Lyude Paul Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_ddi.c | 8 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c

[Intel-gfx] [PATCH 1/3] drm/i915: Fix atomic state leak when resetting HDMI link

Atomic state needs to be put even if the commit was successful. Fixes: dba14b27dd3c ("drm/i915: Reinitialize sink scrambling/TMDS clock ratio on HPD") Reviewed-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Lyude Paul Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel

[Intel-gfx] [PATCH 5/5] drm/i915: Extract gem_init() from modeset_load()

Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 58 - 1 file changed, 35 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 2b5ce764e694..f4163a8bb244 100644 --- a

[Intel-gfx] [PATCH 1/5] drm/i915/vlv: Move czclk to intel_pm

Moving VLV/CHV/BYT czclk to intel_pm as it is a core clock used as base by several other GPU blocks including GT. BSpec: 14370 Cc: Lucas De Marchi Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_display.c | 12 drivers/gpu/drm/i915/intel_pm.c

[Intel-gfx] [PATCH 2/5] drm/i915: Rename i915_load_modeset_init() to i915_modeset_load()

i915_load_modeset_init() sounds horrible also lets rename it so the future cleanup function of it can be easially recognized. Cc: Lucas De Marchi Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions

[Intel-gfx] [PATCH 3/5] drm/i915: Add a cleanup function for i915_modeset_load()

Lets make i915_driver_unload() easier to read by starting to move components initialized by i915_modeset_load() to i915_modeset_unload(). Cc: Lucas De Marchi Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 27 ++- drivers

[Intel-gfx] [PATCH 4/5] drm/i915: Move rawclck, power_domain and irq un/initialization from modeset functions

The initialization of those componentes is required by the GEM/GT not only display so lets move then to a more the appropriate place. Cc: Lucas De Marchi Cc: Jani Nikula Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.c | 39 drivers

[Intel-gfx] [PATCH v4 6/9] drm/i915: Disable PSR2 while getting pipe CRC

c_prepare() and crc_enabled, only setting mode_changed if it can do PSR. v2: Changed commit description to describe that PSR2 inhibit CRC calculations. Cc: Dhinakaran Pandiyan Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_pipe_crc.c | 1 + drivers/gpu/drm/i

[Intel-gfx] [PATCH v4 9/9] drm/i915: Enable PSR2 by default

-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index b237d96db277..116c8b50ee78 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 1/9] drm/i915/psr: Remove PSR2 FIXME

Now we are checking sink capabilities when probing PSR DPCD register and then dynamically checking in if new state is compatible with PSR in, so this FIXME can be dropped. Reviewed-by: Dhinakaran Pandiyan Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915

[Intel-gfx] [PATCH v4 3/9] drm/i915: Compute and commit color features in fastsets

. Reviewed-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Maarten Lankhorst Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

[Intel-gfx] [PATCH v4 5/9] drm/i915/crc: Make IPS workaround generic

changes to the functions that prepares the commit (Ville) Cc: Dhinakaran Pandiyan Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_display.c | 10 -- drivers/gpu/drm/i915/intel_drv.h | 3 +- drivers/gpu/drm/i915/intel_pipe_crc.c | 47

[Intel-gfx] [PATCH v4 7/9] drm/i915: Drop redundant checks to update PSR state

All of this checks are redudant and can be removed as the if bellow already takes care when there is no changes in the state. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 12 1 file changed, 4 insertions(+), 8 deletions

[Intel-gfx] [PATCH v4 2/9] drm/i915/psr: Only lookup for enabled CRTCs when forcing a fastset

expected behavior or not but in the mean time this fix the issue. Cc: Maarten Lankhorst Cc: Dhinakaran Pandiyan Reviewed-by: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers

[Intel-gfx] [PATCH v4 8/9] drm/i915/psr: Set idle frames to maximum while getting pipe CRC

Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_psr.c | 17 +++-- 2 files changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index

[Intel-gfx] [PATCH v4 4/9] drm/i915/psr: Drop test for EDP in CRTC when forcing commit

Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 6175b1d2e0c8..2d9f64c362e2 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915

[Intel-gfx] [PATCH] drm/i915/icl: Remove alpha support protection

i-icl-y.html Reference: https://intel-gfx-ci.01.org/tree/drm-tip/shard-iclb.html Cc: James Ausmus Cc: Jani Saarinen Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Jani Nikula Cc: Ville Syrjälä Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_pci.c | 1 - 1 file changed, 1 deletion(-)

[Intel-gfx] [PATCH v2 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR

TPS4 support was added to PSR because HBR3/PSR spec was not closed when ICL was freezed so if HBR3 was supported by PSR, ICL would already be ready but it was not added to spec so lets always disable TPS4. BSpec: 17524 Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers

[Intel-gfx] [PATCH v2 2/3] drm/i915/psr: Move logic to get TPS registers values to another function

This will make hsw_activate_psr1() more easy to read and will make future modification to TPS registers more easy to review and read. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 56 +++- 1 file changed, 33

[Intel-gfx] [PATCH v2 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time

A new field with the training pattern(TP) wakeup time for PSR2 was added to VBT, so lets use it when available otherwise it will fallback to PSR1 wakeup time. v2: replacing enum to numerical usec time (Jani) BSpec: 20131 Cc: Jani Nikula Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de

[Intel-gfx] [PATCH v3 3/3] drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR

ned-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_psr.c | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 16ce9c609c65..a7697909e0c9 100644 --- a/drivers/gp

[Intel-gfx] [PATCH v3 1/3] drm/i915/vbt: Parse and use the new field with PSR2 TP2/3 wakeup time

A new field with the training pattern(TP) wakeup time for PSR2 was added to VBT, so lets use it when available otherwise it will fallback to PSR1 wakeup time. v2: replacing enum to numerical usec time (Jani) BSpec: 20131 Cc: Jani Nikula Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de

[Intel-gfx] [PATCH v3 2/3] drm/i915/psr: Move logic to get TPS registers values to another function

This will make hsw_activate_psr1() more easy to read and will make future modification to TPS registers more easy to review and read. Cc: Dhinakaran Pandiyan Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_psr.c | 56 +++- 1 file changed, 33

[Intel-gfx] [PATCH v5 3/9] drm/i915: Compute and commit color features in fastsets

. Reviewed-by: Ville Syrjälä Cc: Ville Syrjälä Cc: Maarten Lankhorst Signed-off-by: José Roberto de Souza --- drivers/gpu/drm/i915/intel_display.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c

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