er shot.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 345 ++--
1 file changed, 121 insertions(+), 224 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/inte
v2:
- Make sure cursor allocation stays constant and fixed at the end of
the pipe allocation.
- Fix some watermark level iterators that weren't handling the max
level.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
Signed-off-by: Matt Roper
---
drivers
and put a hardcoded 1.0 value into
the last two entries.
Matt
>
> /* Keep in gen based order, and chronological order within a gen */
>
> --
> 1.9.1
>
> ___
> dri-devel mailing list
> dri-de...@lists.freedesktop.org
>
Try to be more consistent about intel_* types rather than drm_* types
for lower-level driver functions.
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_drv.h | 5 +-
drivers/gpu/drm/i915/intel_display.c | 32 ++---
drivers/gpu/drm/i915/intel_drv.h | 10 +-
drivers/gpu/drm
eful about following that convention. Let's try to be more
consistent about using the intel_* types.
Matt Roper (2):
drm/i915: Use intel_ types more consistently for watermark code
drm/i915: Use intel_ types more consistently for color management code
drivers/gpu/drm/i915/i915_drv.h |
Try to be more consistent about intel_* types rather than drm_* types
for lower-level driver functions. While we're at it, let's also be more
consistent with state variable naming (half of the platforms use the
name 'state' whereas the other half used 'crtc_state'
nsistency between platform types (Ville)
- Drop the crtc parameter to intel_color_check(); we can just pull that
out of the state object.
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/i915_drv.h | 4 +-
drivers/gpu/drm/i915/intel_color.c | 215 +
Try to be more consistent about intel_* types rather than drm_* types
for lower-level driver functions.
v2:
- Also drop the intel_crtc parameter from compute_intermediate_wm()
since we can just extract it from the crtc_state parameter. (Ville)
Signed-off-by: Matt Roper
Reviewed-by: Ville
On Mon, Dec 10, 2018 at 09:31:55PM +0200, Ville Syrjälä wrote:
> On Thu, Dec 06, 2018 at 04:54:01PM -0800, Matt Roper wrote:
> > Try to be more consistent about intel_* types rather than drm_* types
> > for lower-level driver functions. While we're at it, let's also be
lle)
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 376 ++--
1 file changed, 132 insertions(+), 244 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gp
ns can be more accurately bisected to either the different
watermark value (in this patch) or the new DDB allocation (in the next
patch).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers
On Tue, Dec 11, 2018 at 05:59:56PM +0200, Ville Syrjälä wrote:
> On Mon, Dec 10, 2018 at 05:05:43PM -0800, Matt Roper wrote:
...snip...
> >
> > - alloc_size -= total_min_blocks;
> > - cstate->wm.skl.plane_ddb_y[PLANE_CURSOR].start = alloc->end -
> > mini
ns can be more accurately bisected to either the different
watermark value (in this patch) or the new DDB allocation (in the next
patch).
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers
e we need to avoid to a prevent a
div-by-0. (Ville)
- s/DIV_ROUND_UP/DIV64_U64_ROUND_UP/ to prevent 32-bit breakage (Ville)
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pm.c | 381 +++-
e we need to avoid to a prevent a
div-by-0. (Ville)
- s/DIV_ROUND_UP/DIV64_U64_ROUND_UP/ to prevent 32-bit breakage (Ville)
v5:
- Don't forget to move 'start' pointer forward for UV surface when
setting plane DDB boundaries. (Ville)
Cc: Ville Syrjälä
Bugzilla: https://bug
ns can be more accurately bisected to either the different
watermark value (in this patch) or the new DDB allocation (in the next
patch).
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_pm.c | 7 ---
1 file changed, 7 deletions(-)
diff --git a/driver
hievable, don't forget to reset blocks=0
when testing the next lower level (otherwise that one will surely
fail as well). (CI)
Cc: Ville Syrjälä
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105458
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/
s.freedesktop.org/show_bug.cgi?id=108569
> [fdo#108784]: https://bugs.freedesktop.org/show_bug.cgi?id=108784
> [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
> [fdo#108889]: https://bugs.freedesktop.org/show_bug.cgi?id=108889
> [fdo#108948]: https://bugs.freedesktop.or
On Tue, Dec 11, 2018 at 11:25:45AM -0800, Bob Paauwe wrote:
> It's not just GEN9 platforms that allow for pipes to be disabled via
> the DFSM register, but all later platforms as well.
>
> v2: drop pointless parentheses (Ville)
>
> Signed-off-by: Bob Paauwe
Reviewed-by:
userspace-provided LUT doesn't violate hardware requirements.
Cc: Uma Shankar
Cc: Swati Sharma
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_color_mgmt.c | 53
include/drm/drm_color_mgmt.h | 3 +++
2 files changed, 56 insertions(+)
diff --gi
GLK and
ICL (actual degamma support for those two platforms hasn't landed yet,
but there's work in flight by Uma and Swati to add it, so we might as
well get the checks ready early).
Matt Roper (2):
drm: Add color management LUT validation helpers
drm/i915: Validate userspace-provided co
.
Cc: Uma Shankar
Cc: Swati Sharma
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_color.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 1d572e83db7f..041bb5d6a6cd 100644
--- a/drive
t our running block count when trying each lower level, otherwise
all lower levels will fail as well.
Cc: Ville Syrjälä
Fixes: d8e8749802 ("drm/i915: Switch to level-based DDB allocation algorithm
(v5)")
Signed-off-by: Matt Roper
---
After waiting for CI results to come out, I accidental
On Wed, Dec 12, 2018 at 09:23:38PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 12, 2018 at 11:17:20AM -0800, Matt Roper wrote:
> > During DDB allocation, we try to distribute enough blocks for each plane
> > to hit the highest watermark level; if that fails, we retry each lower
&
0895] RDX: RSI: 55c689a05d2e RDI:
>
> <4>[ 13.980916] RBP: 55c689a05d2e R08: R09:
> 0000
> <4>[ 13.980936] R10: 0000 R11: 0246 R12:
>
> <4>[
tarkey's suggestion to combine the
separate helpers into a single function that takes a bitmask of tests to
apply. It also adds an additional LUT size test inspired by the ARM
malidp driver.
Matt Roper (2):
drm: Add color management LUT validation helper (v2)
drm/i915: Validate userspace-
. (stolen from ARM driver)
Cc: Uma Shankar
Cc: Swati Sharma
Cc: Brian Starkey
Signed-off-by: Matt Roper
Reviewed-by(v1): Brian Starkey
---
drivers/gpu/drm/drm_color_mgmt.c | 64
include/drm/drm_color_mgmt.h | 5
2 files changed, 69 inse
forms.
v2:
- Use new API (single check function with bitmask of tests to apply)
- Call helper for our gamma table as well (with no additional tests
specified) so that the table size will be validated.
Cc: Uma Shankar
Cc: Swati Sharma
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_co
u32 supported_ranges,
> > enum drm_color_encoding default_encoding,
> > enum drm_color_range default_range);
> > +
> > +#define DRM_COLOR_LUT_EQUAL_CHANNELS BIT(0)
> > +#define DRM_COLOR_LUT_INCREASING BIT(1)
>
. (stolen from ARM driver)
v3:
- Drop the LUT size check again since
drm_atomic_replace_property_blob_from_id() already covers this for
us. (Alexandru Gheorghe)
Cc: Uma Shankar
Cc: Swati Sharma
Cc: Brian Starkey
Signed-off-by: Matt Roper
Reviewed-by(v1): Brian Starkey
Reviewe
b upload and we don't have any additional hardware
constraints for that LUT.
Cc: Uma Shankar
Cc: Swati Sharma
Signed-off-by: Matt Roper
Reviewed-By: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i
Previous version of the series was here:
https://lists.freedesktop.org/archives/dri-devel/2018-December/200505.html
The only change in this version is dropping the extra LUT size test I
added in v2; Alexandru pointed out that that already gets tested when a
new atomic blob is uploaded.
Matt
(Daniel Vetter)
- s/DRM_COLOR_LUT_INCREASING/DRM_COLOR_LUT_NON_DECREASING/. (Ville)
Cc: Uma Shankar
Cc: Swati Sharma
Cc: Brian Starkey
Cc: Daniel Vetter
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by(v1): Brian Starkey
Reviewed-by: Alexandru Gheorghe
Reviewed-by: Uma Shankar
b upload and we don't have any additional hardware
constraints for that LUT.
Cc: Uma Shankar
Cc: Swati Sharma
Signed-off-by: Matt Roper
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i
rjälä
Signed-off-by: Matt Roper
Reviewed-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_color.c
b/drivers/gpu/drm/i915/intel_color.c
index 37fd9ddf762e..e3ffbb0ad9a6 100644
--- a/
On Fri, Dec 21, 2018 at 01:29:38AM +0530, Uma Shankar wrote:
> Removed crtc state variable for gamma mode as it's redundant
> since currently we have fixed modes on respective hardware
> platforms. This was making this state variable irrelevant.
>
> Credits-to: Matt Roper
>
id cherryview_load_luts(struct intel_crtc_state *crtc_state)
> {
> @@ -649,6 +714,8 @@ void intel_color_init(struct intel_crtc *crtc)
> } else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> dev_priv->display.load_csc_matrix = ilk_load_csc_matrix;
>
hew D
> > Cc: intel-gfx ; Li, Wei C
> > ; dri-devel
> > Subject: Re: [Intel-gfx] [PATCH v3 0/3] CRTC background color
> >
> > Hey,
> >
> > Is there anything missing on the Chrome side to move forward with this
> > series?
> >
> > Stépha
On Fri, Dec 28, 2018 at 12:53:29PM +0100, Daniel Vetter wrote:
> Am Fr., 28. Dez. 2018, 02:09 hat Stéphane Marchesin
> geschrieben:
> > On Thu, Dec 27, 2018 at 4:45 PM Matt Roper
> > wrote:
> > >
> > > On Thu, Dec 27, 2018 at 04:22:28PM -0800, Stéphane Mar
On Fri, Dec 28, 2018 at 06:14:40PM +0100, Daniel Vetter wrote:
> On Fri, Dec 28, 2018 at 5:35 PM Matt Roper wrote:
> >
> > On Fri, Dec 28, 2018 at 12:53:29PM +0100, Daniel Vetter wrote:
> > > Am Fr., 28. Dez. 2018, 02:09 hat Stéphane Marchesin
> > > geschrieben:
to Weston, but I'm not sure what the status of that work is.
Matt Roper (3):
drm/i915: Force background color to black for gen9+ (v2)
drm: Add CRTC background color property (v4)
drm/i915/gen9+: Add support for pipe background color (v4)
drivers/gpu/drm/drm_atomic_uapi.c| 4 +
management transformations that a plane with black pixels would.
v2: Rename register to SKL_BOTTOM_COLOR to more closely follow
bspec naming. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_reg.h | 6 ++
drivers/gpu/drm/i915/intel_disp
l cases such as when writeback
connectors are used (Brian Starkey / Eric Anholt)
Cc: dri-de...@lists.freedesktop.org
Cc: wei.c...@intel.com
Cc: harish.krupo@intel.com
Cc: Ville Syrjälä
Cc: Sean Paul
Cc: Brian Starkey
Cc: Eric Anholt
Cc: Stéphane Marchesin
Cc: Daniel Vetter
Signed-off-by: Matt R
W register write. (Ville)
- Minor parameter rename for consistency. (Ville)
v4:
- Removed use of bgcolor_changed flag.
Cc: dri-de...@lists.freedesktop.org
Cc: wei.c...@intel.com
Cc: harish.krupo@intel.com
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/i915_debug
On Fri, Aug 30, 2019 at 12:27:45AM -0700, Ser, Simon wrote:
> On Thu, 2019-08-29 at 09:47 -0700, Matt Roper wrote:
> > This test performs display updates via COMMIT_ATOMIC, but fails to check
> > that the platform being tested actually supports atomic. This causes
> > fa
On Fri, Aug 30, 2019 at 12:29:25AM -0700, Ser, Simon wrote:
> On Thu, 2019-08-29 at 13:52 -0700, Matt Roper wrote:
> > When choosing a low resolution mode to switch to, we search the
> > connector's mode list for a mode that's small enough that a plane
> > position
har lines to add clarity to
what's going on.
Cc: Maarten Lankhorst
Signed-off-by: Matt Roper
---
tests/kms_panel_fitting.c | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/tests/kms_panel_fitting.c b/tests/kms_panel_fitting.c
index 491e429f..a94229
://bugs.freedesktop.org/show_bug.cgi?id=110854
> [fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
> [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
> [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
>
>
> Participating hosts
On Mon, Sep 02, 2019 at 07:51:41PM +0300, Ville Syrjälä wrote:
> On Fri, Aug 30, 2019 at 03:30:23PM -0700, Matt Roper wrote:
> > Most gen7 and gen8 platforms can't do plane scaling, so we need to
> > ensure the test doesn't try to do plane scaling on those platforms.
e;
> +
> + gen3_assert_iir_is_zero(uncore, TRANS_PSR_IIR(trans));
> + }
> + } else {
> + gen3_assert_iir_is_zero(uncore, EDP_PSR_IIR);
> + }
>
> for_each_pipe(dev_priv, pipe) {
> dev_priv->de_irq_m
> > + val = I915_READ(DP_TP_CTL(port));
> > + val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
> > + val |= DP_TP_CTL_LINK_TRAIN_PAT1;
> > + I915_WRITE(DP_TP_CTL(port), val);
> > + }
> >
l for consistency? That code is specific
to HSW/BDW so it doesn't cause a problem, but there's always the risk
that it might get copy/pasted somewhere else where the direct register
usage is wrong.
Otherwise,
Reviewed-by: Matt Roper
Matt
> ---
> drivers/gpu/drm/i915/display/i
ne EDP_PSR_IIR _MMIO(0x64838)
> -#define EDP_PSR_ERROR(shift) (1 << ((shift) + 2))
> -#define EDP_PSR_POST_EXIT(shift) (1 << ((shift) + 1))
> -#define EDP_PSR_PRE_EN
On Tue, Sep 03, 2019 at 02:53:04PM -0700, Souza, Jose wrote:
> On Tue, 2019-09-03 at 14:42 -0700, Matt Roper wrote:
> > On Thu, Aug 29, 2019 at 02:25:48AM -0700, Lucas De Marchi wrote:
> > > From: José Roberto de Souza
> > >
> > > It was enabling and
+ return false;
> +
> return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> }
> --
> 2.23.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform
rchi
Another approach would be to just convert the switch to a more
traditional if/else ladder as we use pretty much everywhere else in the
driver (which would also allow us to handle stuff like vlv and chv
without an extra level of nesting). But this works too, so
Reviewed-by: Matt Roper
> -
On Wed, Sep 04, 2019 at 04:42:49PM +0300, Jani Nikula wrote:
> On Tue, 09 Jul 2019, Matt Roper wrote:
> > Convert the code that operates directly on gen11 combo PHY's to use the
> > new namespace. Combo PHY registers are those named "ICL_PORT_*" plus
> > ICL_D
ected by checks like
> pipe_config->fec_enable that is only set by intel_dp.
>
> v3 (José):
> - Using intel_crtc_has_dp_encoder() instead of intel_encoder_is_dp()
> (Ville)
>
> Cc: Matt Roper
> Cc: Ville Syrjälä
> Signed-off-by: Lucas De Marchi
Reviewed-by: Matt
On Wed, Sep 04, 2019 at 04:02:40PM -0700, José Roberto de Souza wrote:
> WA 1409120013 is also valid for TGL, so lets check for ">= 11".
>
> BSpec: 52890
>
> Cc: Matt Roper
> Cc: Clinton Taylor
> Signed-off-by: José Roberto de Souza
Reviewed-by: Matt Rop
plies to, the DSI outputs always
have port==phy so we're still passing the same integer values around no
matter which type of enum they belong to..
Cc: Jani Nikula
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/icl_dsi.c | 236 ---
drivers/gpu/drm/i915/displa
ff-by: Matt Roper
---
drivers/gpu/drm/i915/i915_irq.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 135c9ee55e07..6a2012aa28c8 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm
t.
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index c500fc9154c8..b9d53eaee80a 1006
Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
during some power state transitions.
Bspec: 49201
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 7
These new cdclk values should be accounted for in the voltage level
selection (we can use the same voltage level as 307.2 and 312 rather
than bumping up up to the next higher level).
Bspec: 21809
Cc: José Roberto de Souza
Signed-off-by: Matt Roper
---
The EHL and TGL parts of the bspec haven&#
dclks for gen11+")
Cc: José Roberto de Souza
Cc: Lucas De Marchi
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 17 ++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i9
On Fri, Sep 06, 2019 at 02:36:49PM +0300, Ville Syrjälä wrote:
> On Thu, Sep 05, 2019 at 11:13:37AM -0700, Matt Roper wrote:
> > Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
> > TGL runs at refclk/2. The 50MHz croclk/2 is only used by hardware
> &
address this by including a more literal
representation of the bspec tables in the driver and adapting our driver
to parse those tables to get the values they need.
Cc: Ville Syrjälä
Matt Roper (8):
drm/i915: Consolidate bxt/cnl/icl cdclk readout
drm/i915: Use literal representation of cdclk t
The uninitialize flow is the same on all of these platforms, aside from
calculating a different frequency level.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 48 +++---
1 file changed, 14 insertions(+), 34 deletions(-)
diff --git
values or enabling new platforms. Let's just add a form of the
bspec table to the code and then adjust our functions to pull what they
need directly out of the table.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 319 -
drive
The CNL variant of this function is identical to the BXT variant aside
from not needing to handle SSA precharge.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +-
1 file changed, 2 insertions(+), 44 deletions(-)
diff --git
When reading out the BIOS-programmed cdclk state, let's make sure that
the cdclk value is on the valid list for the platform, ensure that the
VCO matches the cdclk, and ensure that the CD2X divider was set
properly.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/di
ssary
sanitization (we now have valid clock frequencies that use this
divider).
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 65 +-
1 file changed, 2 insertions(+), 63 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk
uot;update" makes me think we should be writing to hardware rather than
reading from it.
Cc: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 325 +
1 file changed, 138 insertions(+), 187 deletions(-)
cdclk PLL.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 267 +
1 file changed, 119 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/display/intel_cdclk.c
With all of the cdclk function consolidation, we can cut down on a lot
of platform if/else logic by creating a vfunc that's initialized at
startup.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 76 --
drivers/gpu/drm
On Fri, Sep 06, 2019 at 03:41:42PM -0700, Radhakrishna Sripada wrote:
> Disable CPS aware color pipe by setting chicken bit.
>
> BSpec: 52890
BSpec: 45829
as well ("This bit must be programmed to 1").
Reviewed-by: Matt Roper
> HSDES: 1409142259
>
> Cc: Stua
On Fri, Sep 06, 2019 at 03:46:42PM -0700, Daniele Ceraolo Spurio wrote:
>
>
> On 9/6/19 3:41 PM, Radhakrishna Sripada wrote:
> > Disable CPS aware color pipe by setting chicken bit.
> >
> > BSpec: 52890
> > HSDES: 1409142259
> >
> > Cc: Stuart S
values or enabling new platforms. Let's just add a form of the
bspec table to the code and then adjust our functions to pull what they
need directly out of the table.
v2: Fix comparison when finding best cdclk.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/display/inte
values or enabling new platforms. Let's just add a form of the
bspec table to the code and then adjust our functions to pull what they
need directly out of the table.
v2: Fix comparison when finding best cdclk.
v3: Another logic fix for calc_cdclk.
Cc: Ville Syrjälä
Signed-off-by: Matt Rope
f overflow.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105127
Signed-off-by: Matt Roper
---
tests/kms_rotation_crc.c | 22 --
1 file changed, 8 insertions(+), 14 deletions(-)
diff --git a/tests/kms_rotation_crc.c b/tests/kms_rotation_crc.c
index 668c1732..8f36f
in a cleaner and more future-proof
manner.
Cc: Ville Syrjälä
Matt Roper (8):
drm/i915: Consolidate bxt/cnl/icl cdclk readout
drm/i915: Use literal representation of cdclk tables
drm/i915: Combine bxt_set_cdclk and cnl_set_cdclk
drm/i915: Kill cnl_sanitize_cdclk()
drm/i915: Consolidate
The uninitialize flow is the same on all of these platforms, aside from
calculating a different frequency level.
v2: Reverse platform conditional order for consistency. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display
With all of the cdclk function consolidation, we can cut down on a lot
of platform if/else logic by creating a vfunc that's initialized at
startup.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c
cdclk PLL.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 267 +
1 file changed, 119 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
b/drivers/gpu/drm/i915/di
et impossible inputs; just WARN and return 0.
(Ville)
- Keep a bxt_ prefix on the lookup functions since they're still only
used on bxt+ for now. We can rename them later if we extend this
table-based approach back to older platforms. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Matt Ro
uot;update" makes me think we should be writing to hardware rather than
reading from it.
v2:
- Fix icl_calc_voltage_level() limits. (Ville)
- Use CNL_CDCLK_PLL_RATIO_MASK rather than BXT_DE_PLL_RATIO_MASK on
gen10+ to avoid confusion. (Ville)
Cc: Ville Syrjälä
Suggested-by: Ville Syr
The CNL variant of this function is identical to the BXT variant aside
from not needing to handle SSA precharge.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +-
1 file changed, 2 insertions
ssary
sanitization (we now have valid clock frequencies that use this
divider).
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 65 +-
1 file changed, 2 insertions(+), 63 deletions(-)
diff --git a/drivers/gp
When reading out the BIOS-programmed cdclk state, let's make sure that
the cdclk value is on the valid list for the platform, ensure that the
VCO matches the cdclk, and ensure that the CD2X divider was set
properly.
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Sy
mits. (Ville)
Cc: Ville Syrjälä
Suggested-by: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 325 +
1 file changed, 138 insertions(+), 187 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_c
24mhz refclk. (Ville)
- Don't miss the named initializers on the cnl table. (Ville)
- Represent refclk in table as u16 rather than u32. (Ville)
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
Reviewed-by: Ville Syrjälä
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 303 +++-
for [A,X]BGR888 pixel
> formats.
>
> v2: Fix checkpatch warnings (Lucas)
>
> Cc: Ville Syrjälä
> Cc: Matt Roper
> Cc: Nanley G Chery
> Cc: Jason Ekstrand
> Signed-off-by: Dhinakaran Pandiyan
> Signed-off-by: Lucas De Marchi
> ---
> drivers/gpu/drm/i915/display/int
ktop.org/show_bug.cgi?id=111325
> [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
> [fdo#111330]: https://bugs.freedesktop.org/show_bug.cgi?id=111330
> [fdo#111609]: https://bugs.freedesktop.org/show_bug.cgi?id=111609
> [fdo#99912]: https://bugs.freede
On Wed, Sep 11, 2019 at 04:31:26PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> On tgl/bxt/glk the cdclk bypass frequency depends on the PLL
> reference clock. So let's read out the ref clock before we
> try to compute the bypass clock.
>
> Cc: Matt Roper
&
rdware
> cdclk state as invalid, and we proceed to sanitize it even
> though the hardware may have active pipes and whatnot.
>
> Fix up the mask so we get rid of all three pipe select bits
> and thus hopefully no longer sanitize cdclk when it's already
> correctly program
On Wed, Sep 11, 2019 at 04:31:28PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one
> copy.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/di
o that call
> just fine on older platforms since they leave min_voltage_level[]
> zeroed. Let's rename the function to bxt_compute_min_voltage_level()
> just so it stays consistent with the rest of the naming scheme.
>
> Signed-off-by: Ville Syrjälä
Reviewed-by: Matt Roper
5/cml: Introduce Comet Lake PCH")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111461
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/intel_pch.c | 1 +
drivers/gpu/drm/i915/intel_pch.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pch.c b/drive
On Mon, Sep 16, 2019 at 05:26:10PM -0700, Lucas De Marchi wrote:
> On Mon, Sep 16, 2019 at 4:33 PM Matt Roper wrote:
> >
> > The CMP PCH ID we have in the driver is correct for the CML-U machines we
> > have
> > in our CI system, but the CML-S and CML-H CI machines ap
On Mon, Sep 16, 2019 at 09:50:00PM -0700, Saarinen, Jani wrote:
> HI,
>
> > -Original Message-
> > From: Intel-gfx [mailto:intel-gfx-boun...@lists.freedesktop.org] On Behalf
> > Of Matt
> > Roper
> > Sent: tiistai 17. syyskuuta 2019 3.35
> > T
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