Maarten's review comments and re-ordered the patch
series.
Uma Shankar (3):
drm/i915/icl: Add icl pipe degamma and gamma support
drm/i915/icl: Enable ICL Pipe CSC block
drm/i915/icl: Add degamma and gamma lut size to gen11 caps
drivers/gpu/drm/i915/i915_pci.c| 3 +-
drivers/gpu/drm
ten's review comment.
Uma Shankar (2):
drm/i915/icl: Define Plane Input CSC Coefficient Registers
drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversion
drivers/gpu/drm/i915/i915_reg.h | 217 +++
drivers/gpu/drm/i915/intel_color.c | 49 +++
definition as separate patch
as per Maarten's suggestion.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 217
1 file changed, 217 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69
Maarten's and Ville's review comments and added the
coefficients in a 2D array instead of independent Macros.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 49
drivers/gpu/drm/i915/intel_display.c | 24 +-
d
Maarten's comment. Also addresed a shift
issue with B channel coefficient.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 58
drivers/gpu/drm/i915/intel_display.c | 24 +++
drivers/gpu/drm/i915/intel_drv.h | 2 ++
definition as separate patch
as per Maarten's suggestion.
v3: Removed a redundant 3rd register definition and simplified
the equally spaced register definition by adding an offset as
per Matt's comment.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_
ated to get feedback
on the design and implementation for this feature. In parallel,
I will test this on actual ICL hardware and confirm with planar
formats.
Uma Shankar (2):
drm/i915/icl: Define Plane Input CSC Coefficient Registers
drm/i915/icl: Enable Plane Input CSC for YUV to RGB Conversi
definition as separate patch
as per Maarten's suggestion.
v3: Removed a redundant 3rd Pipe register definition and
simplified the equally spaced register definition by adding an
offset as per Matt's comment.
v4: No Change
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_
olor Handling.
Note: This is currently untested and floated to get feedback
on the design and implementation for this feature. In parallel,
I will test this on actual ICL hardware and confirm with planar
formats.
Uma Shankar (2):
drm/i915/icl: Define Plane Input CSC Coefficient Registers
drm/i9
ded support for Limited Range Color Handling
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 79
drivers/gpu/drm/i915/intel_display.c | 23 ---
drivers/gpu/drm/i915/intel_drv.h | 2 +
3 files changed, 98 insertions(+), 6 del
ded support for Limited Range Color Handling
v5: Fixed Matt and Maarten's review comments.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_color.c | 79
drivers/gpu/drm/i915/intel_display.c | 23 ---
drivers/gpu/drm/i915/intel_drv.h
Color Handling.
v5: Fixed Matt and Maarten's review comments.
Note: This is currently untested and floated to get feedback
on the design and implementation for this feature. In parallel,
I will test this on actual ICL hardware and confirm with planar
formats.
Uma Shankar (2):
drm/i915/ic
definition as separate patch
as per Maarten's suggestion.
v3: Removed a redundant 3rd Pipe register definition and
simplified the equally spaced register definition by adding an
offset as per Matt's comment.
v4: No Change
v5: Renamed the register Macro as per Matt's suggestion.
Sig
perty documentation as suggested by Daniel, Vetter.
v4: Rebase
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 6 ++
drivers/gpu/drm/drm_atomic.c| 9 +
drivers/gpu/drm/drm_atomic_helper.c | 3 +++
drivers/gpu/drm/drm_plane.c
ested by Daniel, Vetter.
v4: Rebase
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 3 +++
drivers/gpu/drm/drm_atomic.c| 10 ++
drivers/gpu/drm/drm_atomic_helper.c | 4
drivers/gpu/drm/drm_plane.c | 12
include/drm/drm_pl
rties
Added property documentation as suggested by Daniel, Vetter.
v4: Rebase
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 9 +
drivers/gpu/drm/drm_atomic.c| 13 +
drivers/gpu/drm/drm_atomic_helper.c | 6 ++
drivers/gpu/drm/drm_pl
umentation as suggested by Daniel, Vetter.
Fixed a rebase fumble which occurred in v2, pointed by Emil Velikov.
v4: Rebase
Uma Shankar (8):
drm: Add Enhanced Gamma LUT precision structure
drm: Add Plane Degamma properties
drm: Add Plane CTM property
drm: Add Plane Gamma properties
d
.
v4: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_plane.c | 19 +++
include/uapi/drm/drm_mode.h | 15 +++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index 6153cbd..cd71fd0 100644
--- a/drivers
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
v4: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_plane.c | 42
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++-
drivers/gpu/drm/i915/i915_reg.h | 25
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
v4: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 4
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i915
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
v4: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h | 5
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h
.
v4: Rebase
v5: Relocated the helper function to drm_color_mgmt.c. Declared
the same in a header file (Alexandru Gheorghe)
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
drivers/gpu/drm/drm_color_mgmt.c | 19 +++
include/drm/drm_color_mgmt.h | 1 +
include
perty documentation as suggested by Daniel, Vetter.
v4: Rebase
v5: Moved property creation to drm_color_mgmt.c file to have all
color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst
ested by Daniel, Vetter.
v4: Rebase
v5: Moved property creation to drm_color_mgmt.c file to have all
color operations consolidated at one place. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst | 3 +++
drivers/gpu/drm/drm_ato
e
all color operations at one place.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
Documentation/gpu/drm-kms.rst | 90 +
drivers/gpu/drm/drm_atomic.c| 13 ++
drivers/gpu/drm/drm_atomic_helper.c | 6 +++
drive
. No logical change.
Signed-off-by: Uma Shankar
Reviewed-by: Alexandru Gheorghe
---
drivers/gpu/drm/drm_color_mgmt.c | 42
include/drm/drm_color_mgmt.h | 5 +
2 files changed, 47 insertions(+)
diff --git a/drivers/gpu/drm/drm_color_mgmt.c b
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
v3: Rebase
v4: Used extended function for LUT extraction (pointed by
Alexandru).
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915
v4: Rebase
v5: Added "Display Color Hardware Pipeline" flow to kernel
documentation as suggested by "Ville Syrjala" and "Brian Starkey".
Moved the property creation to drm_color_mgmt.c file to consolidate
all color operations at one place. Addressed Alexandru's
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
v4: Rebase
v5: Rebase
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 4
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm
.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_plane.c | 19 +++
include/uapi/drm/drm_mode.h | 15 +++
2 files changed, 34 insertions(+)
diff --git a/drivers/gpu/drm/drm_plane.c b/drivers/gpu/drm/drm_plane.c
index a5d1fc7..e706da6 100644
--- a/drivers/gpu/drm
documentation as suggested by Daniel, Vetter.
Fixed a rebase fumble which occurred in v2, pointed by Emil Velikov.
Uma Shankar (8):
drm: Add Enhanced Gamma LUT precision structure
drm: Add Plane Degamma properties
drm: Add Plane CTM property
drm: Add Plane Gamma properties
drm: Define helper
rties
Added property documentation as suggested by Daniel, Vetter.
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 9 +
drivers/gpu/drm/drm_atomic.c| 12
drivers/gpu/drm/drm_atomic_helper.c | 6 ++
drivers/gpu/drm/drm_plane.c
perty documentation as suggested by Daniel, Vetter.
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 6 ++
drivers/gpu/drm/drm_atomic.c| 8
drivers/gpu/drm/drm_atomic_helper.c | 3 +++
drivers/gpu/drm/drm_plane.c | 23 +++
includ
Define helper function to enable Plane color features
to attach plane color properties to plane structure.
v2: Rebase
v3: Modiefied the function to use updated property names.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_plane.c | 42 ++
include
ested by Daniel, Vetter.
Signed-off-by: Uma Shankar
---
Documentation/gpu/drm-kms.rst | 3 +++
drivers/gpu/drm/drm_atomic.c| 10 ++
drivers/gpu/drm/drm_atomic_helper.c | 3 +++
drivers/gpu/drm/drm_plane.c | 12
include/drm/drm_plane.h
Enable and initialize plane color features.
v2: Rebase and some cleanup
v3: Updated intel_plane_color_init to call
drm_plane_color_create_prop function, which will
in turn create plane color properties.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h | 5
Implement Plane Gamma feature for BDW and Gen9 platforms.
v2: Used newly added drm_color_lut_ext structure for enhanced
precision for Gamma LUT entries.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_pci.c | 5 +++-
drivers/gpu/drm/i915/i915_reg.h | 24
Load plane color luts as part of atomic plane updates.
This will be done only if the plane color luts are changed.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 4
drivers/gpu/drm/i915/intel_color.c| 8
drivers/gpu/drm/i915/intel_drv.h
y properly scaling down all the full
range co-efficients with limited range scaling factor.
v2: Fixed Ville's review comments.
v3: Changed input to const and used correct data types as
suggested by Ville
Signed-off-by: Johnson Lin
Signed-off-by: Uma Shankar
Reviewed-by: Ville Syrjä
---
y properly scaling down all the full
range co-efficients with limited range scaling factor.
v2: Fixed Ville's review comments.
v3: Changed input to const and used correct data types as
suggested by Ville
v4: Fixed some missing data type corrections.
Signed-off-by: Johnson Lin
Signed-off-
From: Shashank Sharma
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |1 +
drivers/gpu/drm/i915/intel_display.c
PIPE for MIPI transcoders.
4. BXT needs to program register MIPI_INIT_COUNT for both the ports,
even if only one is being used.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 22 +++
drivers/gpu/drm/i915/intel_dsi.c | 79
call to pre_pll enabled from CRTC modeset function. Nothing needs to be
done as such in CRTC for DSI encoder, as PLL, clock and and transcoder
programming
will be taken care in encoder's pre_enable and pre_pll_enable function.
Signed-off-by: Shashank Sharma
Signed-off-by: U
From: Shashank Sharma
Pick appropriate port control register (BXT or VLV), based on device.
Get the current hw state wrt Mipi port.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |7 ---
1 file changed, 4 insertions(+), 3 deletions
ff-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 10 --
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 35 ++
3 files changed, 44 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ds
dsi_pre_enable to restrict DPIO programming for VLV
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |7 ++
drivers/gpu/drm/i915/intel_dsi.c | 185 --
2 files changed, 144 insertions(+), 48 deletions(-)
diff
for Tx clock
3. Program 8by3 divider to generate Rx clock
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 51 ++
drivers/gpu/drm/i915/intel_dsi.c |3 ++
drivers/gpu/drm/i915/intel_dsi.h |1 +
d
appropriate core pll disable function.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 31 ++-
3 files changed, 32 insertions
_MODE_PWM (0x1b << 24)
Signed-off-by: Vandana Kannan
Signed-off-by: Sunil Kamath
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 28 +++---
drivers/gpu/drm/i915/intel_drv.h |2 +
drivers/gpu/drm/i915/intel_panel.c | 100 ++--
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915
/bxt: get_hw_state for BXT
drm/i915/bxt: get DSI pixelclock
Sunil Kamath (1):
drm/i915/bxt: Modify BXT BLC according to VBT changes
Uma Shankar (1):
drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/i915_reg.h
function programs the calculated clock values on the PLL.
3. intel_enable_dsi_pll
Wrapper function to use same code for multiple platforms. It checks the
platform and calls appropriate core pll enable function.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915
(bxt_dsi_reset_clocks).
4. Moved some part of the vlv clock reset code, in a new function
(vlv_dsi_reset_clocks) maintaining the exact same sequence.
5. Wrapper function to call corresponding reset clock function.
Signed-off-by: Uma Shankar
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915
shank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_ddi.c | 21 -
drivers/gpu/drm/i915/intel_display.c | 21 +++--
drivers/gpu/drm/i915/intel_opregion.c |3 ++-
4 files changed,
d-off-by: Vandana Kannan
Signed-off-by: Sunil Kamath
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 28 +
drivers/gpu/drm/i915/intel_drv.h |2 +
drivers/gpu/drm/i915/intel_panel.c | 76
3 files changed, 81 insertions(+),
ocks as per
Jani's suggestion.
v4: Addressed Jani's review comments.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 62 ++
drivers/gpu/drm/i915/intel_dsi_pll.c | 42 +++
code in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
v4: Making backlight calls generic as per Jani's suggestion.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/int
ode paths in case of DSI encoder calls.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_ddi.c | 83 -
drivers/gpu/drm/i915/intel_display.c | 21 ++---
ixed Jani's review comment wrt util pin enable
Signed-off-by: Vandana Kannan
Signed-off-by: Sunil Kamath
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 28
drivers/gpu/drm/i915/intel_drv.h |2 +
drivers/gpu/drm/i915/intel_panel.c | 83 ++
ode paths in case of DSI encoder calls.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_ddi.c |7 +--
drivers/gpu/drm/i915/intel_display.c | 21 +++--
drivers/gpu/drm/i915/intel_opregion.c |9 +++--
3 files changed,
design.
Uma Shankar (3):
drm/i915/: DSI mode setting fix
drm/i915/bxt: Get pipe timing for BXT DSI
drm/i915/bxt: Fixed dsi enc disable and blank at bootup
drivers/gpu/drm/i915/i915_drv.h |3 +
drivers/gpu/drm/i915/intel_display.c | 161 +++---
2 files
mipi transcoder. Hence this needs special
handling for BXT DSI.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h |3 +++
drivers/gpu/drm/i915/intel_display.c | 27 +++
2 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm
Fixed dsi crtc state. Updated the get config function
and handled the DSI and DDI encoder cases.
BXT DSI have to be handled differently from rest of the encoders.
Reading the port control register to determine if DSI is enabled.
Generalizing it for all existing platforms.
Signed-off-by: Uma
For BXT DSI, vtotal, vactive, hactive registers are different.
Making changes to intel_crtc_mode_get() and get_pipe_timings(),
to read the correct registers for BXT DSI.
Signed-off-by: Uma Shankar
Signed-off-by: Vandana Kannan
---
drivers/gpu/drm/i915/intel_display.c | 48
: Program Tx Rx and Dphy clocks
drm/i915/bxt: DSI disable and post-disable
drm/i915/bxt: get_hw_state for BXT
drm/i915/bxt: get DSI pixelclock
Sunil Kamath (1):
drm/i915/bxt: Modify BXT BLC according to VBT changes
Uma Shankar (2):
drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
From: Shashank Sharma
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
v2: Rebased on latest nightly branch
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |1
appropriate core pll disable function.
v2: Fixed Jani's review comments.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c |
harma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 21
drivers/gpu/drm/i915/intel_dsi.c | 67 --
2 files changed, 78 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
ORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_ddi.c | 10 +-
drivers/gpu/drm/i915/intel_di
d-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 25 -
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 95 +-
4 files ch
dsi_pre_enable to restrict DPIO programming for VLV
v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
code. Fixed the macros to get proper port offsets.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gp
(bxt_dsi_reset_clocks).
4. Moved some part of the vlv clock reset code, in a new function
(vlv_dsi_reset_clocks) maintaining the exact same sequence.
5. Wrapper function to call corresponding reset clock function.
v2: Fixed Jani's review comments.
Signed-off-by: Uma Shankar
Signed-off-by: Sha
for Tx clock
3. Program 8by3 divider to generate Rx clock
v2: Fixed Jani's review comments. Adjusted the Macro defintion as
per convention. Simplified the logic for bit definitions for
MIPI PORT A and PORT C in same registers.
Signed-off-by: Shashank Sharma
Signed-off-by:
From: Shashank Sharma
Pick appropriate port control register (BXT or VLV), based on device.
Get the current hw state wrt Mipi port.
v2: Rebased on latest drm nightly branch.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |6 +++---
1 file
_PWM (0x1b << 24)
v2: Fixed Jani's review comment.
Signed-off-by: Vandana Kannan
Signed-off-by: Sunil Kamath
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 27 ---
drivers/gpu/drm/i915/intel_drv.h |2 +
drive
code in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ds
ned-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |8 ++--
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 35 ++
3 files changed, 42 insertions(+), 2 deletions(-)
di
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
v2: Rebased on latest drm nightly branch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
From: Shashank Sharma
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
v2: Rebased on latest nightly branch
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |1
: get_hw_state for BXT
drm/i915/bxt: get DSI pixelclock
Sunil Kamath (1):
drm/i915/bxt: Modify BXT BLC according to VBT changes
Uma Shankar (3):
drm/i915/bxt: Program Backlight PWM frequency
drm/i915/bxt: Remove DSP CLK_GATE programming for BXT
drm/i915: Added BXT DSI backlight support
appropriate core pll disable function.
v2: Fixed Jani's review comments.
v3: Rebased on latest drm-nightly branch.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm
dsi_pre_enable to restrict DPIO programming for VLV
v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
code. Fixed the macros to get proper port offsets.
v3: Rebased on latest drm-nightly branch. Fixed Jani's review comments.
Signed-off-by: Shashank Sharma
Signed-o
moved a redundant change wrt code comment.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 22
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c |
code in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
v3: Rebased on latest drm-nightly. Fixed Jani's review comments.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 20 +++-
1 file changed, 19 insert
stion.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 110a895..001569b 100644
--- a/drivers/gpu/drm
_PWM (0x1b << 24)
v2: Fixed Jani's review comment.
v3: Split the backight PWM frequency programming into separate patch,
in cases BIOS doesn't initializes it.
Signed-off-by: Vandana Kannan
Signed-off-by: Sunil Kamath
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i
In some cases, BIOS doesn't initializes DSI panel.DSI and
backlight registers are thereby not initialized. Programming
the same in driver backlight setup.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h|3 +++
drivers/gpu/drm/i915/intel_panel.c | 11 +++
2
ned-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |8 ++--
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 35 ++
3 files changed, 42 insertions(+), 2 deletions(-)
di
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
v2: Rebased on latest drm nightly branch.
v3: Fixed Jani's review comments
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |8 +---
1 file changed, 5 insertions(
ORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
v3: Rebased on latest drm-nightly branch. Added a WARN_ON for invalid
encoder.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_dd
ghtly branch. Fixed Jani's review comments.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 21
drivers/gpu/drm/i915/intel_dsi.c | 69 --
2 files changed, 80 insertions(+), 10 deletions(-)
o for consistency with earlier
implementations as per Jani's suggestion.
Signed-off-by: Uma Shankar
Signed-off-by: Shashank Sharma
---
drivers/gpu/drm/i915/intel_dsi.c | 36 +--
drivers/gpu/drm/i915/intel_dsi.h |2 ++
drivers/gpu/drm/i915/intel_dsi_pl
ocks as per
Jani's suggestion.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 62 ++
drivers/gpu/drm/i915/intel_dsi_pll.c | 39 +
2 files changed, 101 insertions(+)
diff --git a
CEA 861.3 spec adds colorimetry data block for HDMI.
Parsing the block to get the colorimetry data from
panel.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_edid.c | 24
include/drm/drm_connector.h |2 ++
2 files changed, 26 insertions(+)
diff --git a
This patch adds a blob property to get HDR metadata
information from userspace. This will be send as part
of AVI Infoframe to panel.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/drm_connector.c |7 +++
include/drm/drm_connector.h | 11 +++
include/drm/drm_mode_config.h
,
generic property design and infoframe handling. This cannot get merged as of
now without
the userspace support in place. This series is not yet tested.
Uma Shankar (9):
drm: Add HDR source metadata property
drm: Add CEA extended tag blocks and HDR bitfield macros
drm: Parse HDR metadata info
Enable writing of HDR metadata infoframe to panel.
The data will be provid by usersapace compositors, based
on blending policies and passsed to driver through a blob
property.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c | 25 +
drivers/video/hdmi.c
Attach HDR metadata property to connector object.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_hdmi.c |2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 41267ff..d8b53d0 100644
--- a/drivers/gpu/drm
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