From: Shashank Sharma
This patch contains following changes:
1. Add BXT MIPI display address base.
2. Call dsi_init from display_setup function.
v2: Rebased on latest nightly branch
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |1
appropriate core pll disable function.
v2: Fixed Jani's review comments.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c |
harma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 21
drivers/gpu/drm/i915/intel_dsi.c | 67 --
2 files changed, 78 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
ORT for non DDI
encoder like DSI for platforms having HAS_DDI as true.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_drv.h |1 +
drivers/gpu/drm/i915/intel_ddi.c | 10 +-
drivers/gpu/drm/i915/intel_di
d-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h | 25 -
drivers/gpu/drm/i915/intel_dsi.c |2 +-
drivers/gpu/drm/i915/intel_dsi.h |2 +-
drivers/gpu/drm/i915/intel_dsi_pll.c | 95 +-
4 files ch
dsi_pre_enable to restrict DPIO programming for VLV
v2: Fixed Jani's review comments. Removed the changes in VLV/CHV
code. Fixed the macros to get proper port offsets.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h |9 +++
drivers/gp
(bxt_dsi_reset_clocks).
4. Moved some part of the vlv clock reset code, in a new function
(vlv_dsi_reset_clocks) maintaining the exact same sequence.
5. Wrapper function to call corresponding reset clock function.
v2: Fixed Jani's review comments.
Signed-off-by: Uma Shankar
Signed-off-by: Sha
for Tx clock
3. Program 8by3 divider to generate Rx clock
v2: Fixed Jani's review comments. Adjusted the Macro defintion as
per convention. Simplified the logic for bit definitions for
MIPI PORT A and PORT C in same registers.
Signed-off-by: Shashank Sharma
Signed-off-by:
From: Shashank Sharma
Pick appropriate port control register (BXT or VLV), based on device.
Get the current hw state wrt Mipi port.
v2: Rebased on latest drm nightly branch.
Signed-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |6 +++---
1 file
_PWM (0x1b << 24)
v2: Fixed Jani's review comment.
Signed-off-by: Vandana Kannan
Signed-off-by: Sunil Kamath
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/i915_reg.h| 27 ---
drivers/gpu/drm/i915/intel_drv.h |2 +
drive
code in this patch. Backlight setup and
enable/disable code for backlight is added in intel_dsi.c.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c | 25 -
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_ds
ned-off-by: Shashank Sharma
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |8 ++--
drivers/gpu/drm/i915/intel_dsi.h |1 +
drivers/gpu/drm/i915/intel_dsi_pll.c | 35 ++
3 files changed, 42 insertions(+), 2 deletions(-)
di
DSP CLK_GATE registers are specific to BYT and CHT.
Avoid programming the same for BXT platform.
v2: Rebased on latest drm nightly branch.
Signed-off-by: Uma Shankar
---
drivers/gpu/drm/i915/intel_dsi.c |9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu
801 - 813 of 813 matches
Mail list logo
