Hi Alex
On Fri, May 9, 2014 at 11:28 PM, Alex Williamson
wrote:
>
>
> Original description:
>
> This series attempts to fix a couple issues we've had outstanding in
> the PCI/IOMMU code for a while. The first issue is with devices that
> use the wrong requester ID for DMA transactions. We
The user of the IOMMU API domain expects to have full control of
the IOVA space for the domain. RMRRs are fundamentally incompatible
with that idea. We can neither map the RMRR into the IOMMU API
domain, nor can we guarantee that the device won't continue DMA with
the area described by the RMRR a
[+cc original lists]
Hi Edward,
On Tue, 2014-05-13 at 15:35 -0700, eddy0596 wrote:
> Hello Alex,
>
> Thanks for working on a fix on this long standing issue. I have applied the
> amd portion of the IOMMU patches against the 3.14.3 kernel and found the
> followings:
> 1) The computer would not bo
On Wed, 2014-05-14 at 12:34 +0200, Joerg Roedel wrote:
> On Sat, May 10, 2014 at 09:03:11AM -0600, Alex Williamson wrote:
> > The expectation is that the kernel and IVRS will produce the same
> > result for topology based aliases while the kernel will also include
> > device specific DMA quirks.
>
Hi,
I'm not sure why you're submitting this, Suravee?
We already agreed that we need the extra mmu_notifier point, proposed by Joerg
back in 2011, to eliminate the race. I had thought we were waiting on that to
be implemented.
From: Joerg Roedel [j...@8
On Wednesday 14 May 2014 11:23:33 Shaik Ameer Basha wrote:
> The current dt binding for Exynos System MMU can be changed, if found
> incompatible with the support for "Generic IOMMU Binding".
> This patch adds a note to the binding documentation stating the same.
>
> Signed-off-by: Shaik Ameer Bas
On Sat, May 10, 2014 at 09:03:11AM -0600, Alex Williamson wrote:
> The expectation is that the kernel and IVRS will produce the same
> result for topology based aliases while the kernel will also include
> device specific DMA quirks.
Is that expectation really true? There are PCIe devices out ther
On Wed, May 14, 2014 at 01:34:12AM -0500, suravee.suthikulpa...@amd.com wrote:
> A low probability race exists with this fix. Translations received
> within the critical section to PTEs which are concurrently being
> invalidated may resolve to stale mappings.
Sorry, no. This patch can cause silent
On Wed, May 14, 2014 at 11:23:33AM +0530, Shaik Ameer Basha wrote:
> .../devicetree/bindings/iommu/samsung,sysmmu.txt |5 +
> 1 file changed, 5 insertions(+)
Applied, thanks.
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