Re: [Patch v3 00/12] Fix AMD IOMMU faults in kdump kernel

CC more people who is interested On 01/26/16 at 06:29pm, Baoquan He wrote: > This is v3 post. Now the situation is patchset test on amd-vi v2 machine > is OK, however still some IO_PAGE_FAULT warning is printed out on v1 > machine. The log will be attached later. > > I didn't figure out what

Re: iommu/arm-smmu-v2 ASID/VMID calculation

On 26/01/16 03:11, Chalamarla, Tirumalesh wrote: one my colleague points out, ASIDPNE also implementation defined. ASIDPNE only covers whether the SMMU's TLBs may ignore broadcast _invalidation_ or not, not lookups. Broadcast TLB lookups are not a thing. Thanks, Tirumalesh. On 1/25/16,

[Patch v3 06/12] iommu/amd: Clean up the useless IOMMU_PTE_U/IOMMU_PTE_FC

In amd-vi spec bit[60:58] are only used to store the bit[14:12] of GCR3. No any other useage is found in several versions of amd-vi spec. So remove them in this patch. Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu.c | 6 +++--- drivers/iommu/amd_iommu_types.h | 2

[Patch v3 09/12] iommu/amd: Don't update the domain information to iommu dev before dev init

Don't update the domain information to the related DTE entry before iommu dev initialization. For this a new member 'domain_updated' is added to iommu_dev_data. Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu.c | 14 +- 1 file changed, 9 insertions(+), 5

[Patch v3 05/12] iommu/amd: change IOMMU_PTE_P to IOMMU_PTE_V

In amd-vi spec the name of bit0 in DTE is V. But in code it's defined as IOMMU_PTE_P. Here change it to IOMMU_PTE_V to make it be consistent with spec. Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu.c | 10 +- drivers/iommu/amd_iommu_types.h | 6 +++--- 2

[Patch v3 03/12] iommu/amd: move dte irq macro defitions to amd_iommu_types.h

These macro definitions are also needed by irq table copy function later, so move them to amd_iommu_types.h. Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu.c | 4 drivers/iommu/amd_iommu_types.h | 5 + 2 files changed, 5 insertions(+), 4 deletions(-) diff

[Patch v3 02/12] iommu/amd: Detect pre enabled translation

Add functions to check whether translation is already enabled in IOMMU. Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu_init.c | 26 ++ drivers/iommu/amd_iommu_proto.h | 4 2 files changed, 30 insertions(+) diff --git

[Patch v3 04/12] iommu/amd: add copy_irq_table function

If irq table exists in old kernel create a new one and copy the content of old irq table to the newly created. Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu.c | 2 +- drivers/iommu/amd_iommu_init.c | 43 +

[Patch v3 12/12] iommu/amd: fix a code bug in do_attach

Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c index dda703b..02c6ed9 100644 --- a/drivers/iommu/amd_iommu.c +++ b/drivers/iommu/amd_iommu.c @@

[Patch v3 10/12] iommu/amd: Update related domain info to dev when dev driver init

Whatever it does to initialize dev to alloc coherent memory or map allocated memory to io addr __map_single need be called. So update the related domain information to its DTE entry and alias when __map_single is firstly called. Signed-off-by: Baoquan He ---

[Patch v3 08/12] iommu/amd: set the device table and re-enable event/cmd buffer

Here several things need be done: 1) Initialize amd_iommu_dev_table because it was set several times since kdump kernel reboot. We don't need the set because we will copy the content from old kernel. 2) Re-enable event/cmd buffer 3) Install the DTE table to reg 4) Flush all caches Signed-off-by:

[Patch v3 07/12] iommu/amd: Add function copy_dev_tables

Add function copy_dev_tables to copy old DTE in 1st kernel to the new DTE table. Since all iommu share the same DTE table the copy only need be done once as long as the physical address of old DTE table is retrieved from iommu reg. Besides the old domain id occupied in 1st kernel need be reserved

[Patch v3 01/12] iommu/amd: Use standard bitmap operation to set bitmap

It will be more readable then the old setting. Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu.c | 2 +- drivers/iommu/amd_iommu_init.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/amd_iommu.c b/drivers/iommu/amd_iommu.c

[Patch v3 11/12] iommu/amd: No need to wait iommu completion if no dte irq entry change

This is a clean up. In get_irq_table() only if DTE entry is changed iommu_completion_wait() need be called. Otherwise no need to do it. Signed-off-by: Baoquan He --- drivers/iommu/amd_iommu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH v8 4/5] iommu/mediatek: Add mt8173 IOMMU driver

This patch adds support for mediatek m4u (MultiMedia Memory Management Unit). Signed-off-by: Yong Wu --- drivers/iommu/Kconfig | 16 + drivers/iommu/Makefile| 1 + drivers/iommu/mtk_iommu.c | 732 ++ 3 files changed,

[PATCH v8 3/5] memory: mediatek: Add SMI driver

This patch add SMI(Smart Multimedia Interface) driver. This driver is responsible to enable/disable iommu and control the power domain and clocks of each local arbiter. Signed-off-by: Yong Wu Tested-by: Philipp Zabel --- drivers/memory/Kconfig

[PATCH v8 2/5] dt-bindings: mediatek: Add smi dts binding

This patch add smi binding document and smi local arbiter header file. Signed-off-by: Yong Wu --- .../memory-controllers/mediatek,smi-common.txt | 24 + .../memory-controllers/mediatek,smi-larb.txt | 25 + include/dt-bindings/memory/mt8173-larb-port.h

[PATCH v8 0/5] MT8173 IOMMU SUPPORT

This patch set adds support for m4u(Multimedia Memory Management Unit), Currently it only support the m4u with 2 levels of pagetable on mt8173. It's also based on Robin Murphy's reposting Short-descriptor v2. Please check the hardware block diagram of Mediatek IOMMU. m4u

[PATCH v8 1/5] dt-bindings: iommu: Add binding for mediatek IOMMU

This patch add mediatek iommu dts binding document. Signed-off-by: Yong Wu Acked-by: Rob Herring --- .../devicetree/bindings/iommu/mediatek,iommu.txt | 68 ++ 1 file changed, 68 insertions(+) create mode 100644

[Patch v3 00/12] Fix AMD IOMMU faults in kdump kernel

This is v3 post. Now the situation is patchset test on amd-vi v2 machine is OK, however still some IO_PAGE_FAULT warning is printed out on v1 machine. The log will be attached later. I didn't figure out what caused the warning, so post them to ask for help. The strategy is unchanged: 1) Copy old

Re: iommu/arm-smmu-v2 ASID/VMID calculation

On Tue, Jan 26, 2016 at 03:11:27AM +, Chalamarla, Tirumalesh wrote: > one my colleague points out, ASIDPNE also implementation defined. It looks pretty well defined to me, despite being a hint: This ASIDPNE indication is only a hint, and an SMMU can ignore it. In particular, if the SMMU

[PATCH v8 5/5] dts: mt8173: Add iommu/smi nodes for mt8173

This patch add the iommu/larbs nodes for mt8173 Signed-off-by: Yong Wu --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 81 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi

[RFC PATCH 2/6] iommu/arm-smmu: Invoke DT probe from arm_smmu_of_setup()

The SMMUv1/SMMUv2 driver is initialized very early using the IOMMU_OF_DECLARE() but the actual platform device is probed via normal DT probing. This patch uses of_platform_device_create() from arm_smmu_of_setup() to ensure that SMMU platform device is probed immediately. Signed-off-by: Anup

[RFC PATCH 4/6] iommu/arm-smmu: Add support for IOMMU_DOMAIN_DMA in SMMUv1/SMMUv2 driver

To allow use of large memory (> 4Gb) with 32bit devices we need to use some kind of iommu for such 32bit devices. This patch extends SMMUv1/SMMUv2 driver to support DMA domains which in-turn will allows us to use iommu based DMA mappings for 32bit devices. Signed-off-by: Anup Patel

[RFC PATCH 0/6] iommu/arm-smmu: Add support for DMA domains and instruction fetch

This patchset adds following to SMMUv1/SMMUv2 driver: 1. Support for domain type IOMMU_DOMAIN_DMA 2. Allow privilege instruction fetchs from MMU masters by having a DT option to treat instruction fetch as data read The patchset is based on '4.5-rc1' tag of linux mainline tree and is available in

[RFC PATCH 5/6] iommu/arm-smmu: Option to treat instruction fetch as data read for SMMUv2

Currently, the SMMU driver by default provides unprivilege read-write permission in page table entries of stage1 page table. For SMMUv2 with aarch64 long descriptor format, a privilege instruction fetch will generate context fault. To allow privilege instruction fetch from a MMU master we need to

[RFC PATCH 3/6] of: iommu: Increment DT node refcount in of_iommu_set_ops()

We are saving pointer to iommu DT node in of_iommu_set_ops() hence we should increment DT node ref count. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Scott Branden --- drivers/iommu/of_iommu.c | 1 + 1 file

[RFC PATCH 1/6] iommu/arm-smmu: Init driver using IOMMU_OF_DECLARE

From: Sricharan R This patch uses IOMMU_OF_DECLARE to register the driver and the iommu_ops. So when master devices of the iommu are registered, of_xlate callback can be used to add the master configurations to the smmu driver. Signed-off-by: Sricharan R

[RFC PATCH 6/6] iommu/arm-smmu: Update bindings document for smmu-inst-as-data DT option

This patch adds info about 'smmu-inst-as-data' DT option in ARM SMMUv1/SMMUv2 driver bindings document. Signed-off-by: Anup Patel Reviewed-by: Ray Jui Reviewed-by: Vikram Prakash Reviewed-by: Scott Branden

RE: [PATCH 1/4] iommu/arm-smmu: Treat all device transactions as unprivileged

Hi Robin, > -Original Message- > From: iommu-boun...@lists.linux-foundation.org [mailto:iommu- > boun...@lists.linux-foundation.org] On Behalf Of Robin Murphy > Sent: 26 January 2016 23:37 > To: will.dea...@arm.com > Cc: iommu@lists.linux-foundation.org;

Re: [PATCH 09/10] vfio-pci: create an iommu mapping for msi address

-passthrough-on-ARM-ARM64/20160126-211921 config: i386-allmodconfig (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=i386 All warnings (new ones prefixed by >>): drivers/vfio/pci/vfio_pci_intrs.c: In function 'vfio_set_mapped_ms

Re: [PATCH 09/10] vfio-pci: create an iommu mapping for msi address

the system] > > url: > https://github.com/0day-ci/linux/commits/Eric-Auger/KVM-PCIe-MSI-passthrough-on-ARM-ARM64/20160126-211921 > config: i386-allmodconfig (attached as .config) > reproduce: > # save the attached .config to linux build tree > make ARCH=

Re: [PATCH v8 4/5] iommu/mediatek: Add mt8173 IOMMU driver

-IOMMU-SUPPORT/20160126-201633 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next config: arm64-allyesconfig (attached as .config) reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross chmod

[PATCH V2 0/8] iommu/amd: enable ACPI hardware ID device support

From: Wan Zongshun There are some devices indentified using ACPI HID format in AMD chip. This patch series enable iommu support for those ACPI HID device, since the existing AMD iommu only supports PCI bus based device. The latest public version of AMD IOMMU specification

[PATCH V2 1/8] iommu/amd: Modify ivhd_header structure to support type 11h and 40h

From: Suravee Suthikulpanit This patch modifies the existing struct ivhd_header, which currently only support IVHD type 0x10, to add new fields from IVHD type 11h and 40h. It also modifies the pointer calculation to allow support for IVHD type 11h and 40h

[PATCH V2 4/8] iommu/amd: Introduces ivrs_acpihid kernel parameter

From: Suravee Suthikulpanit This patch introduces a new kernel parameter, ivrs_acpihid. This is used to override existing ACPI-HID IVHD device entry, or add an entry in case it is missing in the IVHD. Signed-off-by: Wan Zongshun

[PATCH V2 3/8] iommu/amd: Add new map for storing IVHD dev entry type HID

From: Wan Zongshun This patch introduces acpihid_map, which is used to store the new IVHD device entry extracted from BIOS IVRS table. It also provides a utility function add_acpi_hid_device(), to add this types of devices to the map. Signed-off-by: Wan Zongshun

[PATCH V2 2/8] iommu/amd: Use the most comprehensive IVHD type that the driver can support

From: Suravee Suthikulpanit The IVRS in more recent AMD system usually contains multiple IVHD block types (e.g. 0x10, 0x11, and 0x40) for each IOMMU. The newer IVHD types provide more information (e.g. new features specified in the IOMMU spec), while maintain

[PATCH V2 6/8] iommu/amd: Add iommu support for ACPI HID devices

From: Wan Zongshun Current IOMMU driver make assumption that the downstream devices are PCI. With the newly added ACPI-HID IVHD device entry support, this is no longer true. This patch is to add dev type check and to distinguish the pci and acpihid device code path.

[PATCH V2 7/8] iommu/amd: Manage iommu_group for ACPI HID devices

From: Wan Zongshun This patch creates a new function for finding or creating an IOMMU group for acpihid(ACPI Hardware ID) device. The acpihid devices with the same devid will be put into same group and there will have the same domain id and share the same page table.

[PATCH V2 5/8] iommu/amd: Make call-sites of get_device_id aware of its return value

From: Wan Zongshun This patch is to make the call-sites of get_device_id aware of its return value. Signed-off-by: Wan Zongshun --- drivers/iommu/amd_iommu.c | 51 +-- 1 file changed, 41 insertions(+), 10

[PATCH V2 8/8] iommu/amd: Set AMD iommu callbacks for amba bus

From: Wan Zongshun AMD Uart DMA belongs to ACPI HID type device, and its driver is basing on AMBA Bus, need also IOMMU support. This patch is just to set the AMD iommu callbacks for amba bus. Signed-off-by: Wan Zongshun --- drivers/iommu/amd_iommu.c

Re: [PATCH 06/10] vfio: introduce vfio_group_alloc_map_/unmap_free_reserved_iova

-passthrough-on-ARM-ARM64/20160126-211921 config: x86_64-randconfig-s3-01262306 (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): >> ERROR: "alloc_iova" [drivers/vfio/vfio_iom

Re: [PATCH 06/10] vfio: introduce vfio_group_alloc_map_/unmap_free_reserved_iova

the system] > > url: > https://github.com/0day-ci/linux/commits/Eric-Auger/KVM-PCIe-MSI-passthrough-on-ARM-ARM64/20160126-211921 > config: x86_64-randconfig-s3-01262306 (attached as .config) > reproduce: > # save the attached .config to linux build tree > m

Re: [PATCH 10/10] vfio: allow the user to register reserved iova range for MSI mapping

-passthrough-on-ARM-ARM64/20160126-211921 config: x86_64-randconfig-s3-01262306 (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): ERROR: "alloc_iova" [drivers/vfio/vfio_iommu_typ

[PATCH v3 3/3] iommu/io-pgtable: Avoid redundant TLB syncs

In certain unmapping situations it is quite possible to end up issuing back-to-back TLB synchronisations, which at best is a waste of time and effort, and at worst causes some hardware to get rather confused. Whilst the pagetable implementations, or the IOMMU drivers, or both, could keep track of

[PATCH v3 1/3] iommu/io-pgtable: Add ARMv7 short descriptor support

Add a nearly-complete ARMv7 short descriptor implementation, omitting only a few legacy and CPU-centric aspects which shouldn't be necessary for IOMMU API use anyway. Signed-off-by: Yong Wu Signed-off-by: Robin Murphy --- drivers/iommu/Kconfig

[PATCH v3 0/3] io-pgtable ARM short descriptor format

Hi all, As promised, here's v3 based on 4.5-rc1, with all the previous comments addressed other than the logic of split_blk_unmap() - having looked into it, trying to simplify that essentially just pushes the complexity out into map() and complicates the general case. Ultimately it's an awkward

[PATCH v3 2/3] iommu/io-pgtable: Add helper functions for TLB ops

Add some simple wrappers to avoid having the guts of the TLB operations spilled all over the page table implementations, and to provide a point to implement extra common functionality. Acked-by: Will Deacon Acked-by: Laurent Pinchart

Re: [PATCH v8 4/5] iommu/mediatek: Add mt8173 IOMMU driver

On 26/01/16 04:12, Yong Wu wrote: This patch adds support for mediatek m4u (MultiMedia Memory Management Unit). Whilst I can't speak for the hardware specifics, I think we've got the API aspects and general shape of the code looking pretty much right by now - I don't see anything worth

[PATCH 0/4] Miscellaneous ARM SMMU patches

Hi Will, Here's my current "miscellaneous SMMU enhancements" branch for your consideration. Patch #1 solves a subtle corner case that cropped up while exercising stage 1 context formats on the DMA330-MMU500 model; #3 will be wanted fairly soon for DMA ops integration so may as well get some

[PATCH 3/4] iommu/arm-smmu: Support DMA-API domains

With DMA mapping ops provided by the iommu-dma code, only a minimal contribution from the IOMMU driver is needed to create a suitable DMA-API domain for them to use. Implement this for the ARM SMMUs. Signed-off-by: Robin Murphy --- drivers/iommu/arm-smmu-v3.c | 10

[PATCH 1/4] iommu/arm-smmu: Treat all device transactions as unprivileged

The IOMMU API has no concept of privilege so assumes all devices and mappings are equal, and indeed most non-CPU master devices on an AMBA interconnect make little use of the attribute bits on the bus thus by default perform unprivileged data accesses. Some devices, however, believe themselves

[PATCH 2/4] iommu/arm-smmu: Allow disabling unmatched stream bypass

Borrow the disable_bypass parameter from the SMMUv3 driver as a handy debugging/security feature so that unmatched stream IDs (i.e. devices not attached to an IOMMU domain) may be configured to fault. Signed-off-by: Robin Murphy --- drivers/iommu/arm-smmu.c | 32

[PATCH 4/4] iommu/arm-smmu: Use per-context TLB sync as appropriate

TLB synchronisation is a mighty big hammmer to bring down on the transaction stream, typically stalling all in-flight transactions until the sync completes. Since in most cases (except at stage 2 on SMMUv1) a per-context sync operation is available, prefer that over the global operation when

Re: [PATCH 10/10] vfio: allow the user to register reserved iova range for MSI mapping

-passthrough-on-ARM-ARM64/20160126-211921 config: x86_64-randconfig-s3-01270003 (attached as .config) reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All errors (new ones prefixed by >>): drivers/built-in.o: In function `vfio_reserved_binding_r

RE: [PATCH 00/10] KVM PCIe/MSI passthrough on ARM/ARM64

Hello! I'd like just to clarify some things for myself and better wrap my head around it... > On x86 all accesses to the 1MB PA region [FEE0_h - FEF0_000h] are directed > as interrupt messages: accesses to this special PA window directly target the > APIC configuration space and not DRAM,

Re: [PATCH] iommu/arm-smmu: add a shortcut when the @dev_node is NULL

On Wed, 2016-01-20 at 14:46 +, Robin Murphy wrote: > > Of course, the 0.004014s maybe not accurate enough, it is just an > > approximate number. > > A mean and standard deviation of at least, say, 5 runs each with and > without the patch would be considerably more meaningful (even if > still

Re: [PATCH v8 4/5] iommu/mediatek: Add mt8173 IOMMU driver

/MT8173-IOMMU-SUPPORT/20160126-201633 base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next config: arm-allmodconfig (attached as .config) reproduce: wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross

Re: [PATCH v8 2/5] dt-bindings: mediatek: Add smi dts binding

On Tue, Jan 26, 2016 at 12:12:39PM +0800, Yong Wu wrote: > This patch add smi binding document and smi local arbiter header file. > > Signed-off-by: Yong Wu > --- > .../memory-controllers/mediatek,smi-common.txt | 24 + >

Re: [Patch v3 12/12] iommu/amd: fix a code bug in do_attach

This one has been posted, so can be ignored here. On 01/26/16 at 06:29pm, Baoquan He wrote: > Signed-off-by: Baoquan He > --- > drivers/iommu/amd_iommu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/iommu/amd_iommu.c

[PATCH 10/10] vfio: allow the user to register reserved iova range for MSI mapping

The user is allowed to register a reserved IOVA range by using the DMA MAP API and setting the new flag: VFIO_DMA_MAP_FLAG_MSI_RESERVED_IOVA. It provides the base address and the size. This region is stored in the vfio_dma rb tree. At that point the iova range is not mapped to any target address

[PATCH 03/10] vfio_iommu_type1: add reserved binding RB tree management

Legacy dma_list is just used to insert the reserved iova region and check mapping of reserved iova happens in this window. As opposed to other vfio_dma slots, the reserved one is not necessarily mapped. We will need to track which host physical addresses are mapped to reserved IOVA. In that

[PATCH 01/10] iommu: Add DOMAIN_ATTR_MSI_MAPPING attribute

Introduce new DOMAIN_ATTR_MSI_MAPPING domain attribute. If supported, this means the MSI addresses need to be mapped in the IOMMU. ARM SMMUS and FSL PAMU, at least expose this attribute. x86 IOMMUs typically don't expose the attribute since on x86 MSI write transaction addresses always are within

[PATCH 02/10] vfio: expose MSI mapping requirement through VFIO_IOMMU_GET_INFO

This patch allows the user-space to retrieve whether msi write transaction addresses must be mapped. This is returned through the VFIO_IOMMU_GET_INFO API using a new flag: VFIO_IOMMU_INFO_REQUIRE_MSI_MAP. Signed-off-by: Bharat Bhushan Signed-off-by: Eric Auger

[PATCH 05/10] vfio/type1: attach a reserved iova domain to vfio_domain

This patch adds a reserved iova_domain to the vfio_domain struct. This iova domain will enable to allocate iova within the reserved iova region. alloc_reserved_iova_domain makes possible to allocate and initialize this iova domain. The user will be introduced in subsequent patches.

[PATCH 08/10] vfio: introduce vfio_group_require_msi_mapping

This new function enables to know whether msi write transaction addresses must be mapped. Signed-off-by: Eric Auger --- drivers/vfio/vfio.c | 22 ++ drivers/vfio/vfio_iommu_type1.c | 8 include/linux/vfio.h| 2 ++ 3

[PATCH 07/10] vfio: pci: cache the vfio_group in vfio_pci_device

Add a new set_group operation which allows to cache the vfio_group handle within the vfio_pci_device struct. This is useful to do iommu operations from the vfio_pci device. Signed-off-by: Eric Auger --- drivers/vfio/pci/vfio_pci.c | 8

[PATCH 09/10] vfio-pci: create an iommu mapping for msi address

Some platforms require the MSI address programmed in the PCI device to be an IOVA and not a host physical address. This is typically the case for ARM and PowerPC, as opposed to x86. This patch allocates an IOVA page and maps it onto the physical page which contains the target MSI write transaction

[PATCH 00/10] KVM PCIe/MSI passthrough on ARM/ARM64

This series addresses KVM PCIe passthrough with MSI enabled on ARM/ARM64. It pursues the efforts done on [1], [2], [3]. It also aims at covering the same need on some PowerPC platforms. On x86 all accesses to the 1MB PA region [FEE0_h - FEF0_000h] are directed as interrupt messages: accesses

[PATCH 06/10] vfio: introduce vfio_group_alloc_map_/unmap_free_reserved_iova

This patch introduces vfio_group_alloc_map_/unmap_free_reserved_iova and implements corresponding vfio_iommu_type1 operations. alloc_map allows to allocate a new reserved iova page and map it onto the physical page that contains a given PA. It returns the iova that is mapped onto the provided PA.