Re: [PATCH] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168

On Mon, 24 Oct 2016, Marc Zyngier wrote: > On 22/10/16 05:54, Geetha sowjanya wrote: > > diff --git a/kernel/irq/chip.c b/kernel/irq/chip.c > > index be3c34e..6add8da 100644 > > --- a/kernel/irq/chip.c > > +++ b/kernel/irq/chip.c > > @@ -585,6 +585,10 @@ void handle_fasteoi_irq(struct irq_desc

Re: [PATCH 2/4] iommu/arm-smmu: Add pm_runtime/sleep ops

On 21 October 2016 at 11:14, Sricharan R wrote: > The smmu needs to be functional when the respective > master/s using it are active. As there is a device_link > between the master and smmu, the pm runtime ops for the smmu > gets invoked in sync with the master's

Re: [PATCH] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168

Hi Marc, Robin. Thanks for your feedback. I will resend the updated patch soon. Thank you, Geetha. From: Marc Zyngier Sent: Monday, October 24, 2016 7:14:35 PM To: Akula, Geethasowjanya; robin.mur...@arm.com; will.dea...@arm.com;

Re: [PATCH] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168

Geetha, On 22/10/16 05:54, Geetha sowjanya wrote: > From: Tirumalesh Chalamarla > > This patch implements Cavium ThunderX erratum 28168. > > PCI requires stores complete in order. Due to erratum #28168 > PCI-inbound MSI-X store to the interrupt

RE: [PATCH V3 0/8] IOMMU probe deferral support

Hi Marek, Initial post from Laurent Pinchart[1]. This is series calls the dma ops configuration for the devices at a generic place so that it works for all busses. The dma_configure_ops for a device is now called during the device_attach callback just before the probe of

RE: [PATCH v5 6/7] iommu/exynos: Add runtime pm support

Hi Marek, >Hi Sricharan > > >On 2016-10-22 07:50, Sricharan wrote: >> >>> This patch adds runtime pm implementation, which is based on previous >>> suspend/resume code. SYSMMU controller is now being enabled/disabled mainly >> > from the runtime pm callbacks. System sleep callbacks relies on

Re: [PATCH] iommu: arm-smmu-v2: Enable 16 bit ASID

Hi Geetha, On 22/10/16 06:02, Geetha sowjanya wrote: > Support up to 16 bit ASID. This patch enables > 16 bit ASID when supported. Why? "Because we can" is not a compelling rationale. I assume this is actually related to the globally-unique ASID workaround for the TLB sharing erratum, but if

Re: [PATCH V3 0/8] IOMMU probe deferral support

Hi Sricharan, On 2016-10-12 08:24, Sricharan wrote: On 2016-10-04 19:03, Sricharan R wrote: Initial post from Laurent Pinchart[1]. This is series calls the dma ops configuration for the devices at a generic place so that it works for all busses. The dma_configure_ops for a device is now