Re: [PATCH v3] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168

2016-12-20 Thread Akula, Geethasowjanya
On 12/20/2016 03:56 AM, Will Deacon wrote: > On Tue, Dec 20, 2016 at 11:52:58AM +, Marc Zyngier wrote: >> On 20/12/16 11:06, Geetha sowjanya wrote: From: Tirumalesh Chalamarla +#ifdef CONFIG_CAVIUM_ERRATUM_28168 +/* + * Cavium ThunderX

[PATCH] iommu/arm-smmu-v3: Clear prior settings when updating STEs

2016-12-20 Thread Nate Watterson
To prevent corruption of the stage-1 context pointer field when updating STEs, rebuild the entire containing dword instead of clearing individual fields. Signed-off-by: Nate Watterson --- drivers/iommu/arm-smmu-v3.c | 10 ++ 1 file changed, 2 insertions(+), 8

Re: [RFC PATCH] iommu/arm-smmu: Add global SMR masking property

2016-12-20 Thread Rob Herring
On Fri, Dec 16, 2016 at 01:19:29PM +, Robin Murphy wrote: > The current SMR masking support using a 2-cell iommu-specifier is > primarily intended to handle individual masters with large and/or > complex Stream ID assignments; it quickly gets a bit clunky in other SMR > use-cases where we just

Re: [PATCH v3] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168

2016-12-20 Thread David Daney
On 12/20/2016 03:56 AM, Will Deacon wrote: On Tue, Dec 20, 2016 at 11:52:58AM +, Marc Zyngier wrote: On 20/12/16 11:06, Geetha sowjanya wrote: From: Tirumalesh Chalamarla +#ifdef CONFIG_CAVIUM_ERRATUM_28168 +/* + * Cavium ThunderX erratum 28168 + * + * Due

Re: [PATCH 3/4] iommu/arm-smmu: Disable stalling faults for all endpoints

2016-12-20 Thread Will Deacon
On Mon, Dec 19, 2016 at 02:33:36PM +0530, Sricharan wrote: > >On Tue, Dec 06, 2016 at 06:30:21PM -0500, Rob Clark wrote: > >> On Thu, Aug 18, 2016 at 9:05 AM, Will Deacon wrote: > >> > Enabling stalling faults can result in hardware deadlock on poorly > >> > designed systems,

Re: [PATCH v3] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168

2016-12-20 Thread Will Deacon
On Tue, Dec 20, 2016 at 11:52:58AM +, Marc Zyngier wrote: > On 20/12/16 11:06, Geetha sowjanya wrote: > > From: Tirumalesh Chalamarla > > +#ifdef CONFIG_CAVIUM_ERRATUM_28168 > > +/* > > + * Cavium ThunderX erratum 28168 > > + * > > + * Due to erratum #28168

Re: [PATCH v3] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168

2016-12-20 Thread Marc Zyngier
Geetha, On 20/12/16 11:06, Geetha sowjanya wrote: > From: Tirumalesh Chalamarla > > This patch implements Cavium ThunderX erratum 28168. > > PCI requires stores complete in order. Due to erratum #28168 > PCI-inbound MSI-X store to the interrupt controller

[PATCH v3] arm64: SMMU-v2: Workaround for Cavium ThunderX erratum 28168

2016-12-20 Thread Geetha sowjanya
From: Tirumalesh Chalamarla This patch implements Cavium ThunderX erratum 28168. PCI requires stores complete in order. Due to erratum #28168 PCI-inbound MSI-X store to the interrupt controller are delivered to the interrupt controller before older

Re: [PATCH] iommu/arm-smmu-v3: avoid over allocating for l2 stream tables

2016-12-20 Thread Will Deacon
Hi Nate, On Mon, Dec 19, 2016 at 03:26:40PM -0500, Nate Watterson wrote: > Currently, all l2 stream tables are being allocated with space for > (1< physically supports. To avoid allocating memory for inaccessible > stes, this patch

Re: [PATCH] iommu/arm-smmu-v3: prevent corruption of ste stage-1 context ptr

2016-12-20 Thread Will Deacon
Hi Nate, Thanks for the patch. On Mon, Dec 19, 2016 at 03:38:38PM -0500, Nate Watterson wrote: > To ensure that the stage-1 context ptr for an ste points to the > intended context descriptor, this patch adds code to clear away > the stale context ptr value prior to or'ing in the new one. > >