From: Joerg Roedel
Instead of finding the matching IOMMU for a device using
string comparision functions, store the pointer to the
iommu_dev in arch_data during the omap_iommu_add_device
callback and reset it during the omap_iommu_remove_device
callback functions.
Signed-off-by: Joerg Roedel
[s
The OMAP IOMMU driver has added the support for IOMMU groups internally,
and the ISP device is automatically linked to the appropriate IOMMU group.
So, remove the explicit function calls that creates/deletes an iommu_group
and adds the ISP device to this group.
Cc: Laurent Pinchart
Signed-off-by:
Hi Joerg,
I have taken the liberty of refreshing the series you have posted
based on my testing and review comments. My unit tests are passing
now with the series. I have summarized the changes below and also
outlined the changes in each patch.
Laurent,
I cannot test the OMAP3 ISP, so request you
From: Joerg Roedel
Modify the driver to register individual iommus and
establish links between devices and iommus in sysfs.
Signed-off-by: Joerg Roedel
[s-a...@ti.com: fix some cleanup issues during failures]
Signed-off-by: Suman Anna
---
v3 w.r.t v1:
- moved the iommu_device calls in probe a
From: Joerg Roedel
The internal data-structures are scattered over various
header and C files. Consolidate them in omap-iommu.h.
While at this, add the kerneldoc comment for the missing
iommu domain variable and revise the iommu_arch_data name.
Signed-off-by: Joerg Roedel
[s-a...@ti.com: revis
All the supported boards that have OMAP IOMMU devices do support
DT boot only now. So, drop the support for the non-DT legacy-style
devices from the OMAP IOMMU driver. Couple of the fields from the
iommu platform data would no longer be required, so they have also
been cleaned up. The IOMMU platfor
Move the registration of the OMAP IOMMU platform driver before
setting the IOMMU callbacks on the platform bus. This causes
the IOMMU devices to be probed first before the .add_device()
callback is invoked for all registered devices, and allows
the iommu_group support to be added to the OMAP IOMMU
From: Joerg Roedel
Support for IOMMU groups will become mandatory for drivers,
so add it to the omap iommu driver.
Signed-off-by: Joerg Roedel
[s-a...@ti.com: minor error cleanups]
Signed-off-by: Suman Anna
---
v3 w.r.t v1:
- iommu_group_get_for_dev() failure path cleanup code added in
the
On Tue, Apr 11, 2017 at 9:12 PM, Robin Murphy wrote:
> On 11/04/17 15:42, linucher...@gmail.com wrote:
>> From: Linu Cherian
>>
>> Cavium 99xx SMMU implementation doesn't support page 1 register space
>> and PAGE0_REGS_ONLY option will be enabled as an errata workaround.
>
> Ugh :(
>
>> This opti
On 2017/4/12 0:57, Sunil Kovvuri wrote:
On Tue, Apr 11, 2017 at 9:29 PM, Robin Murphy wrote:
On 11/04/17 15:42, linucher...@gmail.com wrote:
From: Linu Cherian
Add SMMuV3 model definitions.
Signed-off-by: Linu Cherian
---
include/acpi/actbl2.h | 5 +
1 file changed, 5 insertions(+)
d
Hi Joerg,
Do you plan to merge this one as urgent?
There's bug created about this issue on rhel, it would be great if it
can be put in next or merged so that we can back port it.
Thanks
Baoquan
On 03/29/17 at 05:00pm, Joerg Roedel wrote:
> From: Joerg Roedel
>
> When booting into a kexec kern
Hi Joerg,
This patch is still causing couple of issues.
Adding Laurent and Sakari to the thread as we do have the OMAP3ISP
driver which would need some changes once the iommu groups are
implemented in the OMAP IOMMU driver. The OMAP3 ISP driver
(drivers/media/platform/omap3isp/isp.c) is currently
Hi Joerg,
On 04/07/2017 09:41 AM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Modify the driver to register individual iommus and
> establish links between devices and iommus in sysfs.
>
> Signed-off-by: Joerg Roedel
> ---
> drivers/iommu/omap-iommu.c | 25 +
> driver
On 04/07/2017 09:41 AM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> Don't leave a stale pointer in case the device continues to
> exist for some more time.
>
> Signed-off-by: Joerg Roedel
Acked-by: Suman Anna
> ---
> drivers/iommu/omap-iommu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
>
On 04/07/2017 09:41 AM, Joerg Roedel wrote:
> From: Joerg Roedel
>
> The internal data-structures are scattered over various
> header and C files. Consolidate them in omap-iommu.h.
>
> Signed-off-by: Joerg Roedel
Acked-by: Suman Anna
[snip]
___
iom
On Tue, Apr 11, 2017 at 9:29 PM, Robin Murphy wrote:
> On 11/04/17 15:42, linucher...@gmail.com wrote:
>> From: Linu Cherian
>>
>> Add SMMuV3 model definitions.
>>
>> Signed-off-by: Linu Cherian
>> ---
>> include/acpi/actbl2.h | 5 +
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/inc
On Tue, Apr 11, 2017 at 05:38:21PM +0100, Robin Murphy wrote:
> On 11/04/17 17:21, Will Deacon wrote:
> > On Tue, Apr 11, 2017 at 04:54:26PM +0100, Robin Murphy wrote:
> >> On 11/04/17 15:42, linucher...@gmail.com wrote:
> >>> From: Geetha
> >>>
> >>> Cavium 99xx SMMU implementation doesn't not su
On Tue, Apr 11, 2017 at 9:13 PM, Robin Murphy wrote:
> On 11/04/17 15:42, linucher...@gmail.com wrote:
>> From: Linu Cherian
>>
>> With implementations supporting only page 0 of register space,
>> resource size can be 64k as well and hence perform size checks
>> based on smmu option PAGE0_REGS_ON
On 11/04/17 17:21, Will Deacon wrote:
> On Tue, Apr 11, 2017 at 04:54:26PM +0100, Robin Murphy wrote:
>> On 11/04/17 15:42, linucher...@gmail.com wrote:
>>> From: Geetha
>>>
>>> Cavium 99xx SMMU implementation doesn't not support unique irq lines for
>>> gerror, eventq and cmdq-sync. USE_SHARED_IR
On 04/11/2017 06:44 AM, Bjorn Helgaas wrote:
[+cc David]
I forgot to mention that I'm also hoping for an ack from David, since
he's listed as the maintainer of the ThunderX drivers.
JC is really leading the development of this particular PCI
implementation, but I am happy to supply my:
Ack
On Tue, Apr 11, 2017 at 9:51 PM, Will Deacon wrote:
> On Tue, Apr 11, 2017 at 04:54:26PM +0100, Robin Murphy wrote:
>> On 11/04/17 15:42, linucher...@gmail.com wrote:
>> > From: Geetha
>> >
>> > Cavium 99xx SMMU implementation doesn't not support unique irq lines for
>> > gerror, eventq and cmdq-
On Tue, Apr 11, 2017 at 08:12:38PM +0530, linucher...@gmail.com wrote:
> From: Linu Cherian
>
> Cavium CN99xx SMMUv3 implementation has two Silicon Erratas.
> 1. Errata ID #74
>SMMU register alias Page 1 is not implemented
> 2. Errata ID #126
>SMMU doesnt support unique IRQ lines for gerr
On Tue, Apr 11, 2017 at 04:54:26PM +0100, Robin Murphy wrote:
> On 11/04/17 15:42, linucher...@gmail.com wrote:
> > From: Geetha
> >
> > Cavium 99xx SMMU implementation doesn't not support unique irq lines for
> > gerror, eventq and cmdq-sync. USE_SHARED_IRQS option enables to use single
> > irq
On 11/04/17 15:42, linucher...@gmail.com wrote:
> From: Linu Cherian
>
> Add SMMuV3 model definitions.
>
> Signed-off-by: Linu Cherian
> ---
> include/acpi/actbl2.h | 5 +
> 1 file changed, 5 insertions(+)
>
> diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
> index 2b4af07..9db
On 11/04/17 15:42, linucher...@gmail.com wrote:
> From: Geetha
>
> Cavium 99xx SMMU implementation doesn't not support unique irq lines for
> gerror, eventq and cmdq-sync. USE_SHARED_IRQS option enables to use single
> irq line for all three interrupts.
AFAICS, there's nothing actually wrong wit
On 04/11/2017 11:27 AM, Jayachandran C wrote:
> On Tue, Apr 11, 2017 at 08:41:25AM -0500, Bjorn Helgaas wrote:
>> I suspect the reason this patch makes a difference is because the
>> current pci_for_each_dma_alias() believes one of those top-level
>> bridges is an alias, and the iterator produces
On 11/04/17 15:42, linucher...@gmail.com wrote:
> From: Linu Cherian
>
> With implementations supporting only page 0 of register space,
> resource size can be 64k as well and hence perform size checks
> based on smmu option PAGE0_REGS_ONLY.
What harm comes of mapping page 1 if we don't access it
On 11/04/17 15:42, linucher...@gmail.com wrote:
> From: Linu Cherian
>
> Cavium 99xx SMMU implementation doesn't support page 1 register space
> and PAGE0_REGS_ONLY option will be enabled as an errata workaround.
Ugh :(
> This option when turned on, replaces all page 1 offsets used for
> EVTQ_P
On 11/04/17 14:41, Bjorn Helgaas wrote:
> [+cc Joerg]
>
> On Tue, Apr 11, 2017 at 07:10:48AM +, Jayachandran C wrote:
>> On Mon, Apr 10, 2017 at 08:28:47PM -0500, Bjorn Helgaas wrote:
>>> Hi Jayachandran,
>>>
>>> On Mon, Apr 03, 2017 at 01:15:04PM +, Jayachandran C wrote:
The Cavium T
On Tue, Apr 11, 2017 at 08:41:25AM -0500, Bjorn Helgaas wrote:
> [+cc Joerg]
>
> On Tue, Apr 11, 2017 at 07:10:48AM +, Jayachandran C wrote:
> > On Mon, Apr 10, 2017 at 08:28:47PM -0500, Bjorn Helgaas wrote:
> > > Hi Jayachandran,
> > >
> > > On Mon, Apr 03, 2017 at 01:15:04PM +, Jayachan
From: Linu Cherian
Add Cavium ThunderX2 SMMUv3 erratas to the errata list.
Signed-off-by: Linu Cherian
---
Documentation/arm64/silicon-errata.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/arm64/silicon-errata.txt
b/Documentation/arm64/silicon-errata.txt
index 10f2ddd
From: Linu Cherian
Add SMMuV3 model definitions.
Signed-off-by: Linu Cherian
---
include/acpi/actbl2.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/acpi/actbl2.h b/include/acpi/actbl2.h
index 2b4af07..9db67d6 100644
--- a/include/acpi/actbl2.h
+++ b/include/acpi/actbl2.h
@@
From: Linu Cherian
Enable SKIP_PREFETCH option for HiSilicon SMMUv3 model.
Enable PAGE0_REGS_ONLY and USE_SHARED_IRQS options for
Cavium 99xx SMMUv3 model.
Signed-off-by: Linu Cherian
---
drivers/iommu/arm-smmu-v3.c | 27 +++
1 file changed, 27 insertions(+)
diff --git
From: Linu Cherian
Cavium 99xx implementation doesn't support second page in SMMU
register space. Hence, resource size is set as 64k for this model.
Signed-off-by: Linu Cherian
---
drivers/acpi/arm64/iort.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/a
From: Geetha
Cavium 99xx SMMU implementation doesn't not support unique irq lines for
gerror, eventq and cmdq-sync. USE_SHARED_IRQS option enables to use single
irq line for all three interrupts.
Signed-off-by: Geetha Sowjanya
---
drivers/iommu/arm-smmu-v3.c | 18 +++---
1 file cha
From: Linu Cherian
With implementations supporting only page 0 of register space,
resource size can be 64k as well and hence perform size checks
based on smmu option PAGE0_REGS_ONLY.
For this, arm_smmu_device_dt_probe/acpi_probe has been moved before
platform_get_resource call, so that smmu opti
From: Linu Cherian
Cavium 99xx SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option will be enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.
Signe
From: Linu Cherian
Cavium CN99xx SMMUv3 implementation has two Silicon Erratas.
1. Errata ID #74
SMMU register alias Page 1 is not implemented
2. Errata ID #126
SMMU doesnt support unique IRQ lines for gerror, eventq and cmdq-sync
The following patchset does software workaround for these t
On Apr 11, 2017 8:48 AM, "Bjorn Helgaas" wrote:
[+cc David]
I forgot to mention that I'm also hoping for an ack from David, since
he's listed as the maintainer of the ThunderX drivers.
Never mind this, Jon pointed out that ThunderX2 is different than
ThunderX. Sorry for the noise, David.
On
[+cc David]
I forgot to mention that I'm also hoping for an ack from David, since
he's listed as the maintainer of the ThunderX drivers.
On Mon, Apr 03, 2017 at 01:15:02PM +, Jayachandran C wrote:
> Hi Bjorn, Alex,
>
> Sending this again (with a trivial fix to author name), please review.
>
[+cc Joerg]
On Tue, Apr 11, 2017 at 07:10:48AM +, Jayachandran C wrote:
> On Mon, Apr 10, 2017 at 08:28:47PM -0500, Bjorn Helgaas wrote:
> > Hi Jayachandran,
> >
> > On Mon, Apr 03, 2017 at 01:15:04PM +, Jayachandran C wrote:
> > > The Cavium ThunderX2 arm64 SoCs (called Broadcom Vulcan e
On Mon, Apr 10, 2017 at 08:28:47PM -0500, Bjorn Helgaas wrote:
> Hi Jayachandran,
>
> On Mon, Apr 03, 2017 at 01:15:04PM +, Jayachandran C wrote:
> > The Cavium ThunderX2 arm64 SoCs (called Broadcom Vulcan earlier), the PCI
> > topology is slightly unusual. For a multi-node system, it looks li
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