Hi Geetha,
On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
Urgh, that's unfortunate. In what way is it broken?
> If using MIDR is not accepted, can we enable errata based on SMMU resource
> size?
> some thin
Hi Geert,
On 02/05/17 19:35, Geert Uytterhoeven wrote:
> Hi Sricharan,
>
> On Fri, Feb 3, 2017 at 4:48 PM, Sricharan R wrote:
>> From: Laurent Pinchart
>>
>> Failures to look up an IOMMU when parsing the DT iommus property need to
>> be handled separately from the .of_xlate() failures to suppor
Hi Robin,
On 5/3/2017 3:24 PM, Robin Murphy wrote:
> Hi Geert,
>
> On 02/05/17 19:35, Geert Uytterhoeven wrote:
>> Hi Sricharan,
>>
>> On Fri, Feb 3, 2017 at 4:48 PM, Sricharan R wrote:
>>> From: Laurent Pinchart
>>>
>>> Failures to look up an IOMMU when parsing the DT iommus property need to
>
On 28/04/17 14:22, Ard Biesheuvel wrote:
> On 28 April 2017 at 14:17, Will Deacon wrote:
>> On Fri, Apr 28, 2017 at 02:14:49PM +0100, Ard Biesheuvel wrote:
>>> On 28 April 2017 at 14:11, Will Deacon wrote:
Hi Ard,
[+ devicetree@]
On Fri, Apr 14, 2017 at 01:43:15PM +0100,
Hi Will,
We will resubmit the patches based on IORT.
Thank you,
Geetha.
On Wed, May 3, 2017 at 3:17 PM, Will Deacon wrote:
> Hi Geetha,
>
> On Tue, May 02, 2017 at 12:01:15PM +0530, Geetha Akula wrote:
>> SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
>
> Urgh, that's
> On 3 May 2017, at 11:32, Robin Murphy wrote:
>
>> On 28/04/17 14:22, Ard Biesheuvel wrote:
>>> On 28 April 2017 at 14:17, Will Deacon wrote:
On Fri, Apr 28, 2017 at 02:14:49PM +0100, Ard Biesheuvel wrote:
> On 28 April 2017 at 14:11, Will Deacon wrote:
> Hi Ard,
>
> [+
Hi,
On 5/3/2017 3:54 PM, Sricharan R wrote:
> Hi Robin,
>
> On 5/3/2017 3:24 PM, Robin Murphy wrote:
>> Hi Geert,
>>
>> On 02/05/17 19:35, Geert Uytterhoeven wrote:
>>> Hi Sricharan,
>>>
>>> On Fri, Feb 3, 2017 at 4:48 PM, Sricharan R
>>> wrote:
From: Laurent Pinchart
Failures t
On Thu, Apr 27, 2017 at 4:43 PM, wrote:
> From: Sunil Goutham
>
> Modified polling on CMDQ consumer similar to how polling is done for TLB SYNC
> completion in SMMUv2 driver. Code changes are done with reference to
>
> 8513c8930069 iommu/arm-smmu: Poll for TLB sync completion more effectively
>
Hi,
There are a lot of messages/threads out there about bad performance
while using AMDs Ryzen with KVM GPU passthrough. It revolves all on
enabling/disabling npt, while enabled overall VM performance is nice but
the GPU performance gives me about 20% (and a lot of drops to zero GPU
usage, wh
From: Simon Xue
This patch makes it possible to compile the rockchip-iommu driver on
ARM64, so that it can be used with 64-bit SoCs equipped with this type
of IOMMU.
Signed-off-by: Simon Xue
Signed-off-by: Shunqian Zheng
Signed-off-by: Tomasz Figa
Reviewed-by: Matthias Brugger
---
drivers/i
On 27/04/17 12:13, sunil.kovv...@gmail.com wrote:
> From: Sunil Goutham
>
> Modified polling on CMDQ consumer similar to how polling is done for TLB SYNC
> completion in SMMUv2 driver. Code changes are done with reference to
>
> 8513c8930069 iommu/arm-smmu: Poll for TLB sync completion more effe
On Wed, May 03, 2017 at 06:49:09PM +0530, Sunil Kovvuri wrote:
> On Thu, Apr 27, 2017 at 4:43 PM, wrote:
> > From: Sunil Goutham
> >
> > Modified polling on CMDQ consumer similar to how polling is done for TLB
> > SYNC
> > completion in SMMUv2 driver. Code changes are done with reference to
> >
On Wed, May 03, 2017 at 04:33:57PM +0100, Robin Murphy wrote:
> On 27/04/17 12:13, sunil.kovv...@gmail.com wrote:
> > From: Sunil Goutham
> >
> > Modified polling on CMDQ consumer similar to how polling is done for TLB
> > SYNC
> > completion in SMMUv2 driver. Code changes are done with referenc
On Wed, May 3, 2017 at 9:07 PM, Will Deacon wrote:
> On Wed, May 03, 2017 at 06:49:09PM +0530, Sunil Kovvuri wrote:
>> On Thu, Apr 27, 2017 at 4:43 PM, wrote:
>> > From: Sunil Goutham
>> >
>> > Modified polling on CMDQ consumer similar to how polling is done for TLB
>> > SYNC
>> > completion i
On Wed, May 03, 2017 at 09:24:13PM +0530, Sunil Kovvuri wrote:
> On Wed, May 3, 2017 at 9:07 PM, Will Deacon wrote:
> > On Wed, May 03, 2017 at 06:49:09PM +0530, Sunil Kovvuri wrote:
> >> On Thu, Apr 27, 2017 at 4:43 PM, wrote:
> >> > From: Sunil Goutham
> >> >
> >> > Modified polling on CMDQ c
On Wed, May 3, 2017 at 9:10 PM, Will Deacon wrote:
> On Wed, May 03, 2017 at 04:33:57PM +0100, Robin Murphy wrote:
>> On 27/04/17 12:13, sunil.kovv...@gmail.com wrote:
>> > From: Sunil Goutham
>> >
>> > Modified polling on CMDQ consumer similar to how polling is done for TLB
>> > SYNC
>> > compl
On Wed, May 3, 2017 at 9:29 PM, Will Deacon wrote:
> On Wed, May 03, 2017 at 09:24:13PM +0530, Sunil Kovvuri wrote:
>> On Wed, May 3, 2017 at 9:07 PM, Will Deacon wrote:
>> > On Wed, May 03, 2017 at 06:49:09PM +0530, Sunil Kovvuri wrote:
>> >> On Thu, Apr 27, 2017 at 4:43 PM, wrote:
>> >> > Fro
On Wed, May 3, 2017 at 10:37 AM, Matthias Ehrenfeuchter wrote:
> Hi,
>
> There are a lot of messages/threads out there about bad performance while
> using AMDs Ryzen with KVM GPU passthrough. It revolves all on
> enabling/disabling npt, while enabled overall VM performance is nice but the
> GPU pe
On Tue, May 2, 2017 at 11:46 PM, Oza Pawandeep wrote:
> current device framework and of framework integration assumes
> dma-ranges in a way where memory-mapped devices define their
> dma-ranges. (child-bus-address, parent-bus-address, length).
>
> of_dma_configure is specifically written to take c
On Tue, May 2, 2017 at 11:46 PM, Oza Pawandeep wrote:
> current device framework and of framework integration assumes
> dma-ranges in a way where memory-mapped devices define their
> dma-ranges. (child-bus-address, parent-bus-address, length).
>
> of_dma_configure is specifically written to take c
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