On Thu, Jun 01, 2017 at 01:28:01PM +0100, Jean-Philippe Brucker wrote:
> On 31/05/17 18:23, Rob Herring wrote:
> > On Wed, May 24, 2017 at 07:01:38PM +0100, Jean-Philippe Brucker wrote:
> >> Address Translation Service (ATS) is an extension to PCIe allowing
> >> endpoints to manage their own IOTLB,
Hi Will/Robin,
Just want to check with you on this again. Do you have a very rough
timeline on when the excessive locking in the IOMMU driver may be fixed
(so we can restore expected up to 95% performance)?
Thanks,
Ray
On 5/31/17 10:32 AM, Ray Jui wrote:
> Hi Will,
>
> On 5/31/17 5:44 AM, Wil
This patch series addresses some performance issues in the AMD IOMMU
driver:
- Reduce the amount of MMIO performed during command submission
- When the command queue is (near) full, only wait till there is enough
room for the command rather than wait for the whole queue to be empty
- Limit the f
As newer, higher speed devices are developed, perf data shows that the
amount of MMIO that is performed when submitting commands to the IOMMU
causes performance issues. Currently, the command submission path reads
the command buffer head and tail pointers and then writes the tail
pointer once the c
Currently if there is no room to add a command to the command buffer, the
driver performs a "completion wait" which only returns when all commands
on the queue have been processed. There is no need to wait for the entire
command queue to be executed before adding the next command.
Update the drive
After reducing the amount of MMIO performed by the IOMMU during operation,
perf data shows that flushing the TLB for all protection domains during
DMA unmapping is a performance issue. It is not necessary to flush the
TLBs for all protection domains, only the protection domains associated
with iova
