Re: [PATCH v2 09/16] driver core: add iommu device fault reporting data

On Thu, Oct 05, 2017 at 04:03:37PM -0700, Jacob Pan wrote: > DMA faults can be detected by IOMMU at device level. Adding a pointer > to struct device allows IOMMU subsystem to report relevant faults > back to the device driver for further handling. > For direct assigned device (or user space

[PATCH] iommu/vt-d: only attempt to cleanup svm page request irq if one assigned

Only try to clean up the svm page request irq if one has been assigned. Also clear pr_irq in the error path if irq request fails. Signed-off-by: Jerry Snitselaar --- drivers/iommu/intel-svm.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git

[PATCH v2 05/16] iommu/vt-d: add iommu invalidate function

This patch adds Intel VT-d specific function to implement iommu passdown invalidate API. The use case is for supporting caching structure invalidation of assigned SVM capable devices. Emulated IOMMU exposes queue invalidation capability and passes down all descriptors from the guest to the

[PATCH v2 16/16] iommu/vt-d: add intel iommu page response function

This patch adds page response support for Intel VT-d. Generic response data is taken from the IOMMU API then parsed into VT-d specific response descriptor format. Signed-off-by: Jacob Pan --- drivers/iommu/intel-iommu.c | 30 ++ 1 file

[PATCH v2 09/16] driver core: add iommu device fault reporting data

DMA faults can be detected by IOMMU at device level. Adding a pointer to struct device allows IOMMU subsystem to report relevant faults back to the device driver for further handling. For direct assigned device (or user space drivers), guest OS holds responsibility to handle and respond per device

[PATCH v2 08/16] iommu: introduce device fault data

Device faults detected by IOMMU can be reported outside IOMMU subsystem. This patch intends to provide a generic device fault data such that device drivers can communicate IOMMU faults without model specific knowledge. The assumption is that model specific IOMMU driver can filter and handle most

[PATCH v2 13/16] iommu/intel-svm: notify page request to guest

If the source device of a page request has its PASID table pointer bond to a guest, the first level page tables are owned by the guest. In this case, we shall let guest OS to manage page fault. This patch uses the IOMMU fault notification API to send notifications, possibly via VFIO, to the guest

[PATCH v2 11/16] iommu/vt-d: use threaded irq for dmar_fault

Currently, dmar fault IRQ handler does nothing more than rate limited printk, no critical hardware handling need to be done in IRQ context. Convert it to threaded IRQ would allow fault processing that requires process context. e.g. find out offending device based on source ID in the fault rasons.

[PATCH v2 14/16] iommu/intel-svm: replace dev ops with fault report API

With the introduction of generic IOMMU device fault reporting API, we can replace the private fault callback functions with standard function and event data. Signed-off-by: Jacob Pan --- drivers/iommu/intel-svm.c | 7 +-- include/linux/intel-svm.h | 20

[PATCH v2 07/16] iommu/vt-d: assign PFSID in device TLB invalidation

When SRIOV VF device IOTLB is invalidated, we need to provide the PF source SID such that IOMMU hardware can gauge the depth of invalidation queue which is shared among VFs. This is needed when device invalidation throttle (DIT) capability is supported. Signed-off-by: Jacob Pan

[PATCH v2 10/16] iommu: introduce device fault report API

Traditionally, device specific faults are detected and handled within their own device drivers. When IOMMU is enabled, faults such as DMA related transactions are detected by IOMMU. There is no generic reporting mechanism to report faults back to the in-kernel device driver or the guest OS in case

[PATCH v2 01/16] iommu: introduce bind_pasid_table API function

Virtual IOMMU was proposed to support Shared Virtual Memory (SVM) use in the guest: https://lists.gnu.org/archive/html/qemu-devel/2016-11/msg05311.html As part of the proposed architecture, when an SVM capable PCI device is assigned to a guest, nested mode is turned on. Guest owns the first level

[PATCH v2 12/16] iommu/vt-d: report unrecoverable device faults

Currently, when device DMA faults are detected by IOMMU the fault reasons are printed but the driver of the offending device is involved in fault handling. This patch uses per device fault reporting API to send fault event data for further processing. Offending device is identified by the source

[PATCH v2 03/16] iommu: introduce iommu invalidate API function

From: "Liu, Yi L" When an SVM capable device is assigned to a guest, the first level page tables are owned by the guest and the guest PASID table pointer is linked to the device context entry of the physical IOMMU. Host IOMMU driver has no knowledge of caching

[PATCH v2 06/16] iommu/vt-d: move device_domain_info to header

Allow both intel-iommu.c and dmar.c to access device_domain_info. Prepare for additional per device arch data used in TLB flush function Signed-off-by: Jacob Pan --- drivers/iommu/intel-iommu.c | 18 -- include/linux/intel-iommu.h | 19

[PATCH v2 04/16] iommu/vt-d: support flushing more TLB types

Signed-off-by: Jacob Pan --- drivers/iommu/dmar.c| 53 ++--- drivers/iommu/intel-iommu.c | 3 ++- include/linux/intel-iommu.h | 10 +++-- 3 files changed, 60 insertions(+), 6 deletions(-) diff --git

[PATCH v2 02/16] iommu/vt-d: add bind_pasid_table function

Add Intel VT-d ops to the generic iommu_bind_pasid_table API functions. The primary use case is for direct assignment of SVM capable device. Originated from emulated IOMMU in the guest, the request goes through many layers (e.g. VFIO). Upon calling host IOMMU driver, caller passes guest PASID

[PATCH v2 00/16] IOMMU driver support for SVM virtualization

Hi All, Shared virtual memory (SVM) space between devices and applications can reduce programming complexity and enhance security. To enable SVM in the guest, i.e. shared guest application address space and physical device DMA address, IOMMU driver must provide some new functionalities. This

Re: [PATCH v8 1/5] Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801

On Wed, Sep 27, 2017 at 02:32:37PM +0100, Shameer Kolothum wrote: > From: John Garry > > The HiSilicon erratum 161010801 describes the limitation of HiSilicon > platforms hip06/hip07 to support the SMMU mappings for MSI transactions. > > On these platforms, GICv3 ITS

Re: [PATCH] iommu/arm-smmu-v3: Ensure we sync STE when only changing config field

On 05/10/17 17:49, Will Deacon wrote: > The SMMUv3 architecture permits caching of data structures deemed to be > "reachable" by the SMU, which includes STEs marked as invalid. When > transitioning an STE to a bypass/fault configuration at init or detach > time, we mistakenly elide the

[PATCH] iommu/arm-smmu-v3: Ensure we sync STE when only changing config field

The SMMUv3 architecture permits caching of data structures deemed to be "reachable" by the SMU, which includes STEs marked as invalid. When transitioning an STE to a bypass/fault configuration at init or detach time, we mistakenly elide the CMDQ_OP_CFGI_STE operation in some cases, therefore

Re: [RFC v2 2/4] iommu/arm-smmu-v3: Add tlbi_on_map option

Hi Will, On 23/08/2017 18:42, Will Deacon wrote: > Hi Eric, > > On Wed, Aug 23, 2017 at 02:36:53PM +0200, Auger Eric wrote: >> On 23/08/2017 12:25, Will Deacon wrote: >>> On Tue, Aug 22, 2017 at 10:09:15PM +0300, Michael S. Tsirkin wrote: On Fri, Aug 18, 2017 at 05:49:42AM +0300, Michael S.

Re: [PATCH v8 3/5] iommu/of: Add msi address regions reservation helper

On 05/10/17 14:08, John Garry wrote: > On 05/10/2017 13:44, Robin Murphy wrote: >> On 05/10/17 13:37, John Garry wrote: >>> On 05/10/2017 12:07, Robin Murphy wrote: On 04/10/17 14:50, Lorenzo Pieralisi wrote: > On Wed, Oct 04, 2017 at 12:22:04PM +0100, Marc Zyngier wrote: >> On

Re: [PATCH v8 3/5] iommu/of: Add msi address regions reservation helper

On 05/10/2017 13:44, Robin Murphy wrote: On 05/10/17 13:37, John Garry wrote: On 05/10/2017 12:07, Robin Murphy wrote: On 04/10/17 14:50, Lorenzo Pieralisi wrote: On Wed, Oct 04, 2017 at 12:22:04PM +0100, Marc Zyngier wrote: On 27/09/17 14:32, Shameer Kolothum wrote: From: John Garry

Re: [PATCH v8 3/5] iommu/of: Add msi address regions reservation helper

On 05/10/17 12:57, Will Deacon wrote: > On Thu, Oct 05, 2017 at 12:07:26PM +0100, Robin Murphy wrote: >> On 04/10/17 14:50, Lorenzo Pieralisi wrote: >>> On Wed, Oct 04, 2017 at 12:22:04PM +0100, Marc Zyngier wrote: On 27/09/17 14:32, Shameer Kolothum wrote: > From: John Garry

Re: [PATCH v8 3/5] iommu/of: Add msi address regions reservation helper

On 05/10/17 13:37, John Garry wrote: > On 05/10/2017 12:07, Robin Murphy wrote: >> On 04/10/17 14:50, Lorenzo Pieralisi wrote: >>> On Wed, Oct 04, 2017 at 12:22:04PM +0100, Marc Zyngier wrote: On 27/09/17 14:32, Shameer Kolothum wrote: > From: John Garry >

Re: [PATCH v8 3/5] iommu/of: Add msi address regions reservation helper

On 05/10/2017 12:07, Robin Murphy wrote: On 04/10/17 14:50, Lorenzo Pieralisi wrote: On Wed, Oct 04, 2017 at 12:22:04PM +0100, Marc Zyngier wrote: On 27/09/17 14:32, Shameer Kolothum wrote: From: John Garry On some platforms msi-controller address regions have to be

Re: [PATCH v8 3/5] iommu/of: Add msi address regions reservation helper

On Thu, Oct 05, 2017 at 12:07:26PM +0100, Robin Murphy wrote: > On 04/10/17 14:50, Lorenzo Pieralisi wrote: > > On Wed, Oct 04, 2017 at 12:22:04PM +0100, Marc Zyngier wrote: > >> On 27/09/17 14:32, Shameer Kolothum wrote: > >>> From: John Garry > >>> > >>> On some platforms

Re: [PATCH v8 3/5] iommu/of: Add msi address regions reservation helper

On 04/10/17 14:50, Lorenzo Pieralisi wrote: > On Wed, Oct 04, 2017 at 12:22:04PM +0100, Marc Zyngier wrote: >> On 27/09/17 14:32, Shameer Kolothum wrote: >>> From: John Garry >>> >>> On some platforms msi-controller address regions have to be excluded >>> from normal IOVA

Re: [PATCH] dt-bindings: iommu: ipmmu-vmsa: Use generic node name

On Wed, Oct 04, 2017 at 02:33:08PM +0200, Geert Uytterhoeven wrote: > Use the preferred generic node name in the example. > > Signed-off-by: Geert Uytterhoeven Reviewed-by: Simon Horman ___ iommu

Re: Task based virtual address spaces

Hi Jordan, On 04/10/17 20:43, Jordan Crouse wrote: > Trying to start back up the conversation about multiple address > spaces for IOMMU devices. If you will remember Jean-Philippe posted > some patches back in February for SVM on arm-smmu-v3. > > For quite some time the downstream Snapdragon