On Tue, Oct 17, 2017 at 12:11:55PM -0400, Jim Quinlan wrote:
> My understanding is that dma_pfn_offset is that it is a single
> constant offset from RAM, in our case, to map to PCIe space.
Yes.
> But in
> my commit message I detail how our PCIe controller presents memory
> with multiple regions w
Please keep everyone on CC for all the patches, othervise they are
complete unreviable and will be ignored.
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This patch adds support for the Intel IPU v3 as found
on Skylake and Kaby Lake SoCs. The driver has a dependency
on the firmware binary to function properly.
Signed-off-by: Yong Zhi
Signed-off-by: Tomasz Figa
---
drivers/media/pci/intel/ipu3/Kconfig | 17 +
drivers/media/pci/intel/ipu3/Makefi
From: Tomasz Figa
This patch adds driver to support IPU3-specific
MMU-aware memory alloc/free and sg mapping functions.
Signed-off-by: Tomasz Figa
Signed-off-by: Yong Zhi
---
drivers/media/pci/intel/ipu3/Kconfig | 7 +
drivers/media/pci/intel/ipu3/Makefile | 2 +-
drivers/media
From: Tomasz Figa
IPU3 is capable to deal with a virtual address space with
a dedicated MMU. The driver supports address translation
from virtual(IPU3 internal) to 39 bit wide physical(system).
Build has dependency on exported symbols from:
https://patchwork.kernel.org/patch/9825939/>
Signed-o
This patchset adds support for the Intel IPU3 (Image Processing Unit)
ImgU which is essentially a modern memory-to-memory ISP. It implements
raw Bayer to YUV image format conversion as well as a large number of
other pixel processing algorithms for improving the image quality.
Meta data formats ar
On Mon, Oct 16, 2017 at 5:23 AM, Jean-Philippe Brucker
wrote:
> On 13/10/17 20:10, Rob Herring wrote:
>> On Fri, Oct 06, 2017 at 02:31:39PM +0100, Jean-Philippe Brucker wrote:
>>> On ARM systems, some platform devices behind an IOMMU may support stall
>>> and PASID features. Stall is the ability t
On Tue, Oct 17, 2017 at 4:14 AM, Christoph Hellwig wrote:
> Just took a quick look over this and I basically agree with the comments
> from Robin.
>
> What I don't understand is why you're even trying to do all these
> hacky things.
>
> It seems like the controller should simply set dma_pfn_offset
From: amd
The extent of pages specified when applying a reserved region should
include up to the last page of the range, but not the page following
the range.
Signed-off-by: Gary R Hook
---
drivers/iommu/amd_iommu.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers
In case of error, the function iommu_group_get() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should be
replaced with NULL test.
Fixes: 3ae47292024f ("iommu/ipmmu-vmsa: Add new IOMMU_DOMAIN_DMA ops")
Signed-off-by: Wei Yongjun
---
drivers/iommu/ipmmu-vmsa.c | 2
Hi Robin,
On 2017-10-13 12:48, Robin Murphy wrote:
On 13/10/17 09:15, Marek Szyprowski wrote:
On 2017-10-11 15:56, Robin Murphy wrote:
xHCI requires that data buffers do not cross 64KB boundaries (and are
thus at most 64KB long as well) - whilst xhci_queue_{bulk,isoc}_tx()
already split their
On Tue, Oct 17, 2017 at 10:17:01AM +0200, Christoph Hellwig wrote:
> Looks fine:
>
> Reviewed-by: Christoph Hellwig
>
> Greg, do you want to take this or should I queue it up in the
> dma-mapping tree?
You can take it, thanks!
Acked-by: Greg Kroah-Hartman
_
Looks fine:
Reviewed-by: Christoph Hellwig
Greg, do you want to take this or should I queue it up in the
dma-mapping tree?
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Just took a quick look over this and I basically agree with the comments
from Robin.
What I don't understand is why you're even trying to do all these
hacky things.
It seems like the controller should simply set dma_pfn_offset for
each device hanging off it, and all the supported architectures
sh
Hi Shimoda-san,
CC iommu
On Tue, Oct 17, 2017 at 9:30 AM, Yoshihiro Shimoda
wrote:
> Since the commit de3ee99b097d ("mmc: Delete bounce buffer handling")
> deletes the bounce buffer handling, a request data size will be referred
> to max_{req,seg}_size instead of MMC_QUEUE_BOUNCESZ (64k bytes).
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