Hi Linus,
As Joerg mentioned[1], he's out on paternity leave through the end of
the year and I'm filling in for him in the interim. Thanks,
Alex
[1] https://lkml.org/lkml/2017/10/22/72
The following changes since commit ce76353f169a6471542d999baf3d29b121dce9c0:
iommu/amd: Finish TLB flush
On 13/11/17 16:57, Jacob Pan wrote:
> On Mon, 13 Nov 2017 13:06:24 +
> Jean-Philippe Brucker wrote:
>
>> On 10/11/17 22:18, Jacob Pan wrote:
>>> On Fri, 10 Nov 2017 13:54:59 +
>>> Jean-Philippe Brucker wrote:
>>>
On
On Mon, 13 Nov 2017 13:06:24 +
Jean-Philippe Brucker wrote:
> On 10/11/17 22:18, Jacob Pan wrote:
> > On Fri, 10 Nov 2017 13:54:59 +
> > Jean-Philippe Brucker wrote:
> >
> >> On 09/11/17 19:36, Jacob Pan wrote:
> >>> On
On Mon, 13 Nov 2017 13:19:50 +
Jean-Philippe Brucker wrote:
> On 11/11/17 00:00, Jacob Pan wrote:
> > On Fri, 10 Nov 2017 13:54:59 +
> > Jean-Philippe Brucker wrote:
> >
> >> /*
> >> * Note: I tried to synthesize what I
On 11/11/17 00:00, Jacob Pan wrote:
> On Fri, 10 Nov 2017 13:54:59 +
> Jean-Philippe Brucker wrote:
>
>> /*
>> * Note: I tried to synthesize what I believe would be useful to
>> device
>> * drivers and guests, with regards to the kind of faults that the ARM
On 10/11/17 22:18, Jacob Pan wrote:
> On Fri, 10 Nov 2017 13:54:59 +
> Jean-Philippe Brucker wrote:
>
>> On 09/11/17 19:36, Jacob Pan wrote:
>>> On Tue, 7 Nov 2017 11:38:50 +
>>> Jean-Philippe Brucker wrote:
>>>
I
>
> In this case even though hardware supports PASID, BIND flow fails.
It should fail, since we're reserving PASID 0 for non-PASID transactions with
S1DSS=0b10. In addition, the SMMUv3 specification does not allow using PASID
with a single entry. See the description of S1CDMax in 5.2