Hi,
I am analyzing network performance with intel-iommu enabled.
And found that running with iommu=pt, for every dma map/unmap it
executes this code:
/*
* At boot time, we don't yet know if devices will be 64-bit
capable.
* Assume that they will — if they turn out not to be,
On 03/15/2018 08:58 AM, Joerg Roedel wrote:
On Wed, Mar 14, 2018 at 06:04:44PM -0500, Gary R Hook wrote:
Gary R Hook (5):
iommu/amd - Add debugfs support
iommu/amd - Add a 'verbose' switch for IOMMU debugfs
iommu/amd - Add a README variable for the IOMMU debugfs
iommu
On Tue, Mar 20, 2018 at 03:48:11PM +0900, Magnus Damm wrote:
> From: Magnus Damm
>
> Update the IPMMU DT binding documentation to include the r8a77965 compat
> string for the IPMMU devices included in the R-Car M3-N SoC.
>
> Signed-off-by: Magnus Damm
> ---
>
> Documentation/devicetree/bindin
On Sat, Mar 24, 2018 at 04:05:45PM -0400, Konrad Rzeszutek Wilk wrote:
> > > > Otherwise we might get unused symbol warnings for configs that built
> > > > swiotlb.c only for use by xen-swiotlb.c and that don't otherwise select
> > > > CONFIG_DMA_DIRECT_OPS, which is possible on arm.
> > > >
> > >
On 26/03/18 13:31, Harsh Jain wrote:
On 26-03-2018 17:15, Robin Murphy wrote:
Hi Harsh,
On 26/03/18 10:55, Harsh Jain wrote:
Hi,
Can we add offset to dma address received from IOMMU in
scatter/Gather list before sending it to H/W.
Address to HW = sg_dma_address(sg) + offset, where 0 < off
Stage 1 input addresses are effectively 64-bit in SMMUv3 anyway, so
really all that's involved is letting io-pgtable know the appropriate
upper bound for T0SZ.
Signed-off-by: Robin Murphy
---
v3: Fix IDR5.VAX being a 2-bit field, and slight reorganisation of the
stage 1 IAS logic. Since cons
As with registers, use GENMASK and the bitfield accessors consistently
for table fields, to save some lines and ease maintenance a little. This
also catches a subtle off-by-one wherein bit 5 of CD.T0SZ was missing.
Signed-off-by: Robin Murphy
---
v3: New
drivers/iommu/arm-smmu-v3.c | 147 +
Implement SMMUv3.1 support for 52-bit physical addresses. Since a 52-bit
OAS implies 64KB translation granule support, permitting level 1 block
entries there is simple, and the rest is just extending address fields.
Tested-by: Nate Watterson
Signed-off-by: Robin Murphy
---
v3: No change
drive
As with registers and tables, use GENMASK and the bitfield accessors
consistently for queue fields, to save some lines and ease maintenance
a little. This now leaves everything in a nice state where all named
field definitions expect to be used with bitfield accessors (although
since single-bit fie
Bring io-pgtable-arm in line with the ARMv8.2-LPA feature allowing
52-bit physical addresses when using the 64KB translation granule.
This will be supported by SMMUv3.1.
Tested-by: Nate Watterson
Signed-off-by: Robin Murphy
---
v3: 64K-granule-specific logic in iopte_to_paddr() makes it much mo
Hi all,
Here's a v3 with most of the additional cleanup as discussed, which makes
the diffstat look pretty horrific, but I think it does work out for the
better in the end. I did write a further patch converting "(1 << x)" into
"BIT(x)", but comes out as a +70/-70 diff of pure churn which somehow
The FIELD_{GET,PREP} accessors provided by linux/bitfield.h allow us to
define multi-bit register fields solely in terms of their bit positions
via GENMASK(), without needing explicit *_SHIFT and *_MASK definitions.
As well as the immediate reduction in lines of code, this avoids the
awkwardness of
Before trying to add the SMMUv3.1 support for 52-bit addresses, make
things bearable by cleaning up the various address mask definitions to
use GENMASK_ULL() consistently. The fact that doing so reveals (and
fixes) a latent off-by-one in Q_BASE_ADDR_MASK only goes to show what a
jolly good idea it
On 26-03-2018 17:15, Robin Murphy wrote:
> Hi Harsh,
>
> On 26/03/18 10:55, Harsh Jain wrote:
>> Hi,
>>
>> Can we add offset to dma address received from IOMMU in scatter/Gather list
>> before sending it to H/W.
>>
>> Address to HW = sg_dma_address(sg) + offset, where 0 < offset <
>> sg_dma_le
On 26-03-2018 17:15, Robin Murphy wrote:
> Hi Harsh,
>
> On 26/03/18 10:55, Harsh Jain wrote:
>> Hi,
>>
>> Can we add offset to dma address received from IOMMU in scatter/Gather list
>> before sending it to H/W.
>>
>> Address to HW = sg_dma_address(sg) + offset, where 0 < offset <
>> sg_dma_len
Hi Harsh,
On 26/03/18 10:55, Harsh Jain wrote:
Hi,
Can we add offset to dma address received from IOMMU in scatter/Gather list
before sending it to H/W.
Address to HW = sg_dma_address(sg) + offset, where 0 < offset < sg_dma_len(sg).
sg_dma_address() should already account for sg->offset (i
Hi,
Can we add offset to dma address received from IOMMU in scatter/Gather list
before sending it to H/W.
Address to HW = sg_dma_address(sg) + offset, where 0 < offset < sg_dma_len(sg).
I need this operation to make sure our H/W does not receives entry of size
greater than 2K.
Regards
Harsh
Hi Daniel,
Thanks for your reply.
On 03/26/2018 02:31 PM, Daniel Kurtz wrote:
>+struct rk_iommudata {
>+ struct rk_iommu *iommu;
>+};
Why do we need this struct? Can't we just assign a pointer to struct
rk_iommu directly to dev->archdata.iommu?
hmmm, i was trying to add more device re
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