On Fri, Jan 11, 2019 at 8:33 PM Souptick Joarder wrote:
>
> Previouly drivers have their own way of mapping range of
> kernel pages/memory into user vma and this was done by
> invoking vm_insert_page() within a loop.
>
> As this pattern is common across different drivers, it can
> be generalized b
On Mon, Jan 21, 2019 at 11:35:30AM +0530, Vivek Gautam wrote:
> On Sun, Jan 20, 2019 at 5:31 AM Will Deacon wrote:
> > On Thu, Jan 17, 2019 at 02:57:18PM +0530, Vivek Gautam wrote:
> > > Adding a device tree option for arm smmu to enable non-cacheable
> > > memory for page tables.
> > > We already
On Sat, 19 Jan 2019, Christoph Hellwig wrote:
> [full quote deleted, please take a little more care when quoting]
>
> On Fri, Jan 18, 2019 at 04:44:23PM -0800, Stefano Stabellini wrote:
> > > #ifdef CONFIG_XEN
> > > - if (xen_initial_domain()) {
> > > - dev->archdata.dev_dma_ops = dev->dm
The pull request you sent on Mon, 21 Jan 2019 10:45:42 +0100:
> git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
> tags/iommu-fixes-v5.0-rc3
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/52e60b754438f34d23348698534e9ca63cd751d7
Thank you!
--
Deet-doot-
On Sat, Jan 19, 2019 at 11:46:22AM -0700, Logan Gunthorpe wrote:
> > Instead of having two tiny wrappers I'd just revert
> > 964f2311a6862f1fbcc044d0828ad90030928b7f if we need to pass a real
> > physical address now.
>
> Ok, I can resubmit this with that cleanup. Should I do it in two commits
> (
On 21/01/2019 11:51, Pierre Morel wrote:
> On 18/01/2019 14:51, Jean-Philippe Brucker wrote:
>> Hi Pierre,
>>
>> On 18/01/2019 13:29, Pierre Morel wrote:
>>> On 17/01/2019 14:02, Robin Murphy wrote:
On 15/01/2019 17:37, Pierre Morel wrote:
> The s390 iommu can only allow DMA transactions b
On Mon, Jan 21, 2019 at 02:52:16PM +, Robin Murphy wrote:
> Installing the appropriate non-IOMMU DMA ops in arm_iommu_detch_device()
> serves the case where IOMMU-aware drivers choose to control their own
> mapping but still make DMA API calls, however it also affects the case
> when the arch c
On 21/01/2019 14:24, Ard Biesheuvel wrote:
On Mon, 21 Jan 2019 at 14:56, Robin Murphy wrote:
On 21/01/2019 13:36, Ard Biesheuvel wrote:
On Mon, 21 Jan 2019 at 14:25, Robin Murphy wrote:
On 21/01/2019 10:50, Ard Biesheuvel wrote:
On Mon, 21 Jan 2019 at 11:17, Vivek Gautam wrote:
Hi,
O
Installing the appropriate non-IOMMU DMA ops in arm_iommu_detch_device()
serves the case where IOMMU-aware drivers choose to control their own
mapping but still make DMA API calls, however it also affects the case
when the arch code itself tears down the mapping upon driver unbinding,
where the ops
Hello Christoph,
Thanks for your reply. I successfully compiled a kernel (uImage) for the
X5000 from your Git 'powerpc-dma.6-debug' (both patches) today.
It detects the SATA hard disk drive and boots without any problems. I
will test the first patch in next days.
Thanks for your help,
Chri
On Mon, 21 Jan 2019 at 14:56, Robin Murphy wrote:
>
> On 21/01/2019 13:36, Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 14:25, Robin Murphy wrote:
> >>
> >> On 21/01/2019 10:50, Ard Biesheuvel wrote:
> >>> On Mon, 21 Jan 2019 at 11:17, Vivek Gautam
> >>> wrote:
>
> Hi,
>
> >>
Hi Angelo,
On 18.01.2019 23:50, Angelo Dureghello wrote:
> Hi Laurentiu,
>
> On Fri, Jan 18, 2019 at 12:06:23PM +0200, Laurentiu Tudor wrote:
>> This mapping needs to be created in order for slave dma transfers
>> to work on systems with SMMU. The implementation mostly mimics the
>> one in pl330
On 21/01/2019 13:36, Ard Biesheuvel wrote:
On Mon, 21 Jan 2019 at 14:25, Robin Murphy wrote:
On 21/01/2019 10:50, Ard Biesheuvel wrote:
On Mon, 21 Jan 2019 at 11:17, Vivek Gautam wrote:
Hi,
On Mon, Jan 21, 2019 at 12:56 PM Ard Biesheuvel
wrote:
On Mon, 21 Jan 2019 at 06:54, Vivek Gaut
On 21/01/2019 05:53, Vivek Gautam wrote:
A number of arm_smmu_domain's attributes can be assigned based
on the iommu domains's attributes. These local attributes better
be managed by a bitmap.
So remove boolean flags and move to a 32-bit bitmap, and enable
each bits separtely.
Signed-off-by: Viv
On Mon, 21 Jan 2019 at 14:25, Robin Murphy wrote:
>
> On 21/01/2019 10:50, Ard Biesheuvel wrote:
> > On Mon, 21 Jan 2019 at 11:17, Vivek Gautam
> > wrote:
> >>
> >> Hi,
> >>
> >>
> >> On Mon, Jan 21, 2019 at 12:56 PM Ard Biesheuvel
> >> wrote:
> >>>
> >>> On Mon, 21 Jan 2019 at 06:54, Vivek Gau
On 21/01/2019 10:50, Ard Biesheuvel wrote:
On Mon, 21 Jan 2019 at 11:17, Vivek Gautam wrote:
Hi,
On Mon, Jan 21, 2019 at 12:56 PM Ard Biesheuvel
wrote:
On Mon, 21 Jan 2019 at 06:54, Vivek Gautam wrote:
Qualcomm SoCs have an additional level of cache called as
System cache, aka. Last le
On 17/01/2019 09:27, Vivek Gautam wrote:
From Robin's comment [1] about touching TCR configurations -
"TBH if we're going to touch the TCR attributes at all then we should
probably correct that sloppiness first - there's an occasional argument
for using non-cacheable pagetables even on a cohere
On 18/01/2019 13:29, Pierre Morel wrote:
On 17/01/2019 14:02, Robin Murphy wrote:
On 15/01/2019 17:37, Pierre Morel wrote:
The s390 iommu can only allow DMA transactions between the zPCI device
entries start_dma and end_dma.
Let's declare the regions before start_dma and after end_dma as
reser
On 18/01/2019 14:51, Jean-Philippe Brucker wrote:
Hi Pierre,
On 18/01/2019 13:29, Pierre Morel wrote:
On 17/01/2019 14:02, Robin Murphy wrote:
On 15/01/2019 17:37, Pierre Morel wrote:
The s390 iommu can only allow DMA transactions between the zPCI device
entries start_dma and end_dma.
...
Hi,
On 18/01/2019 15:51, Michael S. Tsirkin wrote:
>
> On Tue, Jan 15, 2019 at 12:19:52PM +, Jean-Philippe Brucker wrote:
>> Implement the virtio-iommu driver, following specification v0.9 [1].
>>
>> This is a simple rebase onto Linux v5.0-rc2. We now use the
>> dev_iommu_fwspec_get() helper
On Mon, 21 Jan 2019 at 11:17, Vivek Gautam wrote:
>
> Hi,
>
>
> On Mon, Jan 21, 2019 at 12:56 PM Ard Biesheuvel
> wrote:
> >
> > On Mon, 21 Jan 2019 at 06:54, Vivek Gautam
> > wrote:
> > >
> > > Qualcomm SoCs have an additional level of cache called as
> > > System cache, aka. Last level cache
Hi,
On Mon, Jan 21, 2019 at 12:56 PM Ard Biesheuvel
wrote:
>
> On Mon, 21 Jan 2019 at 06:54, Vivek Gautam
> wrote:
> >
> > Qualcomm SoCs have an additional level of cache called as
> > System cache, aka. Last level cache (LLC). This cache sits right
> > before the DDR, and is tightly coupled w
Hi Linus,
The following changes since commit bfeffd155283772bbe78c6a05dec7c0128ee500c:
Linux 5.0-rc1 (2019-01-06 17:08:20 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu.git
tags/iommu-fixes-v5.0-rc3
for you to fetch changes up to e8
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