> -邮件原件-
> 发件人: Jerry Snitselaar [mailto:jsnit...@redhat.com]
> 发送时间: 2019年12月20日 17:23
> 收件人: Jim,Yan
> 抄送: j...@8bytes.org; iommu@lists.linux-foundation.org;
> linux-ker...@vger.kernel.org
> 主题: Re: [PATCH] iommu/vt-d: Don't reject nvme host due to scope mismatch
>
> On Fri Dec 20 19, j
On Sat, 21 Dec 2019, Tom Murphy wrote:
> This patchset converts the intel iommu driver to the dma-iommu api.
>
> While converting the driver I exposed a bug in the intel i915 driver
> which causes a huge amount of artifacts on the screen of my
> laptop. You can see a picture of it here:
> https://
On 2019-12-23 10:37 am, Jani Nikula wrote:
On Sat, 21 Dec 2019, Tom Murphy wrote:
This patchset converts the intel iommu driver to the dma-iommu api.
While converting the driver I exposed a bug in the intel i915 driver
which causes a huge amount of artifacts on the screen of my
laptop. You can
On Mon, 23 Dec 2019, Robin Murphy wrote:
> On 2019-12-23 10:37 am, Jani Nikula wrote:
>> On Sat, 21 Dec 2019, Tom Murphy wrote:
>>> This patchset converts the intel iommu driver to the dma-iommu api.
>>>
>>> While converting the driver I exposed a bug in the intel i915 driver
>>> which causes a h
Hi,
On 2019/12/23 15:59, Jim,Yan wrote:
-邮件原件-
发件人: Jerry Snitselaar [mailto:jsnit...@redhat.com]
发送时间: 2019年12月20日 17:23
收件人: Jim,Yan
抄送: j...@8bytes.org; iommu@lists.linux-foundation.org;
linux-ker...@vger.kernel.org
主题: Re: [PATCH] iommu/vt-d: Don't reject nvme host due to scope mism
From: Joerg Roedel
The iommu variable in set_device_exclusion_range() us unused
now and causes a compiler warning. Remove it.
Fixes: 387caf0b759a ("iommu/amd: Treat per-device exclusion ranges as r/w
unity-mapped regions")
Signed-off-by: Joerg Roedel
---
drivers/iommu/amd_iommu_init.c | 2 --
Hi, Greg
On 2019/12/16 上午11:08, Zhangfei Gao wrote:
Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
provide Shared Virtual Addressing (SVA) between accelerators and processes.
So accelerator can access any data structure of the main cpu.
This differs from the data sha
This is a note to let you know that I've just added the patch titled
iommu: set group default domain before creating direct mappings
to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch
This is a note to let you know that I've just added the patch titled
iommu/vt-d: Allocate reserved region for ISA with correct permission
to the 5.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the p
Use devm_platform_ioremap_resource() to simplify code, which
contains platform_get_resource, devm_request_mem_region and
devm_ioremap.
Signed-off-by: Yangtao Li
---
drivers/virtio/virtio_mmio.c | 15 +++
1 file changed, 3 insertions(+), 12 deletions(-)
diff --git a/drivers/virtio/vi
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li
---
drivers/iommu/omap-iommu.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/iommu/omap-iommu.c b/drivers/iommu/omap-iommu.c
index be551cc34be4..297c1be7ecb0 100644
--- a/drivers/iom
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li
---
drivers/iommu/exynos-iommu.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/iommu/exynos-iommu.c b/drivers/iommu/exynos-iommu.c
index 186ff5cc975c..42d8407267ef 100644
--- a/drive
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li
---
drivers/iommu/ipmmu-vmsa.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/iommu/ipmmu-vmsa.c b/drivers/iommu/ipmmu-vmsa.c
index d02edd2751f3..3124e28fee85 100644
--- a/drivers/iom
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li
---
drivers/iommu/mtk_iommu_v1.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/iommu/mtk_iommu_v1.c b/drivers/iommu/mtk_iommu_v1.c
index e93b94ecac45..3d6bb08b2a54 100644
--- a/drive
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li
---
drivers/iommu/rockchip-iommu.c | 6 +-
1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
index b33cdd5aad81..c6d50396f4c2 100644
---
Use devm_platform_ioremap_resource() to simplify code.
Signed-off-by: Yangtao Li
---
drivers/iommu/qcom_iommu.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
index 52f38292df5b..bf94d4d67da4 100644
--- a/drivers/iom
Please ignore this patch.
Thx!
___
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu
On 12/17/19 2:19 PM, Chen, Yian wrote:
Regardless, I have two other patches in this series that could resolve
the problem for me and probably other people. I'd just like at least
one of the three patches to get merged so that my machine boots when
the original commit f036c7fa0ab6 ("iommu/vt-d:
On 2019-12-16 22:07, Jordan Crouse wrote:
Attempt to enable split pagetables if the arm-smmu driver supports it.
This will move the default address space from the default region to
the address range assigned to TTBR1. The behavior should be transparent
to the driver for now but it gets the defaul
> -邮件原件-
> 发件人: Lu Baolu [mailto:baolu...@linux.intel.com]
> 发送时间: 2019年12月23日 21:05
> 收件人: Jim,Yan ; Jerry Snitselaar
> 抄送: iommu@lists.linux-foundation.org; linux-ker...@vger.kernel.org
> 主题: Re: 答复: [PATCH] iommu/vt-d: Don't reject nvme host due to scope
> mismatch
>
> Hi,
>
> On 2019
We expect devices with endpoint scope to have normal PCI headers,
and devices with bridge scope to have bridge PCI headers. However
Some PCI devices may be listed in the DMAR table with bridge scope,
even though they have a normal PCI header. Add a quirk flag for
those special devices.
Cc: Roland
Hi Jim,
On 2019/12/24 11:24, Jim,Yan wrote:
-邮件原件-
发件人: Lu Baolu [mailto:baolu...@linux.intel.com]
发送时间: 2019年12月23日 21:05
收件人: Jim,Yan ; Jerry Snitselaar
抄送: iommu@lists.linux-foundation.org; linux-ker...@vger.kernel.org
主题: Re: 答复: [PATCH] iommu/vt-d: Don't reject nvme host due to sco
This checks whether a domain should use the first level page
table for map/unmap and marks it in the domain structure.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 39 +
1 file changed, 39 insertions(+)
diff --git a/drivers/iommu/intel-iommu.c b/
This adds the Intel VT-d specific callback of setting
DOMAIN_ATTR_NESTING domain attribution. It is necessary
to let the VT-d driver know that the domain represents
a virtual machine which requires the IOMMU hardware to
support nested translation mode. Return success if the
IOMMU hardware suports n
Intel VT-d in scalable mode supports two types of page tables for
IOVA translation: first level and second level. The IOMMU driver
can choose one from both for IOVA translation according to the use
case. This sets up the pasid entry if a domain is selected to use
the first-level page table for iova
First-level translation may map input addresses to 4-KByte pages,
2-MByte pages, or 1-GByte pages. Support for 4-KByte pages and
2-Mbyte pages are mandatory for first-level translation. Hardware
support for 1-GByte page is reported through the FL1GP field in
the Capability Register.
Signed-off-by:
When software has changed first-level tables, it should invalidate
the affected IOTLB and the paging-structure-caches using the PASID-
based-IOTLB Invalidate Descriptor defined in spec 6.5.2.4.
Signed-off-by: Lu Baolu
---
drivers/iommu/dmar.c| 41 +++
drivers/iomm
Export page table internals of the domain attached to each device.
Example of such dump on a Skylake machine:
$ sudo cat /sys/kernel/debug/iommu/intel/domain_translation_struct
[ ... ]
Device :00:14.0 with pasid 0 @0x15f3d9000
IOVA_PFNPML5E PML4E
0x8ce
First-level translation restricts the input-address to a canonical
address (i.e., address bits 63:N have the same value as address
bit [N-1], where N is 48-bits with 4-level paging and 57-bits with
5-level paging). (section 3.6 in the spec)
This makes first level IOVA canonical by using IOVA with
Current intel_pasid_setup_first_level() use 5-level paging for
first level translation if CPUs use 5-level paging mode too.
This makes sense for SVA usages since the page table is shared
between CPUs and IOMMUs. But it makes no sense if we only want
to use first level for IOVA translation. Add PASI
Intel VT-d in scalable mode supports two types of page tables
for DMA translation: the first level page table and the second
level page table. The first level page table uses the same
format as the CPU page table, while the second level page table
keeps compatible with previous formats. The softwar
After we make all map/unmap paths support first level page table.
Let's turn it on if hardware supports scalable mode.
Signed-off-by: Lu Baolu
---
drivers/iommu/intel-iommu.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/int
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