Some hardware variants contain a system level cache or the last level
cache(llc). This cache is typically a large block which is shared by multiple
clients on the SOC. GPU uses the system cache to cache both the GPU data
buffers(like textures) as well the SMMU pagetables. This helps with
improved r
The last level system cache can be partitioned to 32 different slices
of which GPU has two slices preallocated. One slice is used for caching GPU
buffers and the other slice is used for caching the GPU SMMU pagetables.
This patch talks to the core system cache driver to acquire the slice handles,
c
From: Jordan Crouse
Everywhere an IOMMU object is created by msm_gpu_create_address_space
the IOMMU device is attached immediately after. Instead of carrying around
the infrastructure to do the attach from the device specific code do it
directly in the msm_iommu_init() function. This gets it out
This patch calls the right function to destroy the iommu domain as well
as free the associated iommu structure there by facilitating proper
clean up of resources upon failure of creating an address space.
Signed-off-by: Sharat Masetty
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +-
1 file chan
From: Jordan Crouse
Pass the propposed io_pgtable_cfg to the implementation specific
init_context() function to give the implementation an opportunity to
to modify it before it gets passed to io-pgtable.
Signed-off-by: Jordan Crouse
Signed-off-by: Sai Prakash Ranjan
---
drivers/iommu/arm-smmu
The register read-modify-write construct is generic enough
that it can be used by other subsystems as needed, create
a more generic rmw() function and have the gpu_rmw() use
this new function.
Signed-off-by: Sharat Masetty
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 8 +++
From: Vivek Gautam
Add iommu domain attribute for using system cache aka last level
cache on QCOM SoCs by client drivers like GPU to set right
attributes for caching the hardware pagetables into the system cache.
Signed-off-by: Vivek Gautam
Co-developed-by: Sai Prakash Ranjan
Signed-off-by: Sa
From: Jordan Crouse
Refactor how address space initialization works. Instead of having the
address space function create the MMU object (and thus require separate but
equal functions for gpummu and iommu) use a single function and pass the
MMU struct. Make the generic code cleaner by using target
Hi Will, Robin,
While analyzing an arm64 issue in interrupt handling for NVMe [0], we
have noticed a worryingly high CPU utilization in the SMMU driver.
The background is that we may get CPU lockup for high-throughput NVMe
testing, and we noticed that disabling the SMMU during testing avoid
Hi Krzysztof,
On 12/31/19 2:07 AM, Krzysztof Kozlowski wrote:
> On Tue, Dec 31, 2019 at 03:43:39PM +0800, kbuild test robot wrote:
>> Hi Krzysztof,
>>
>> I love your patch! Perhaps something to improve:
>>
>> [auto build test WARNING on iommu/next]
>> [also build test WARNING on v5.5-rc4]
>> [if y
On 12/30/19 11:26 AM, Krzysztof Kozlowski wrote:
> Print size_t as %zu or %zx to fix -Wformat warnings when compiling on
> 64-bit platform (e.g. with COMPILE_TEST):
>
> drivers/iommu/omap-iommu.c: In function ‘flush_iotlb_page’:
> drivers/iommu/omap-iommu.c:437:47: warning:
> forma
Hi Roland,
Jim proposed another solution.
https://lkml.org/lkml/2019/12/23/653
Does this work for you?
Best regards,
baolu
On 1/2/20 10:25 AM, Roland Dreier wrote:
We saw more devices with the same mismatch quirk. So maintaining them in
a quirk table will make it more readable and maintainab
12 matches
Mail list logo
