On Mon 09 Dec 07:07 PST 2019, Thierry Reding wrote:
> From: Thierry Reding
>
Sorry for the slow response on this, finally got the time to go through
this in detail and try it out on some Qualcomm boards.
> On some platforms, the firmware will setup hardware to read from a given
> region of
Hi,
On 2020/2/27 19:57, Russell King wrote:
On the LX2160A, there are lots (about 160) of IOMMU messages produced
during boot; this is excessive. Reduce the severity of these messages
to debug level.
Signed-off-by: Russell King
---
drivers/iommu/iommu.c | 4 ++--
1 file changed, 2
On Tue, Feb 25, 2020 at 07:08:02PM +0100, Cornelia Huck wrote:
> On Mon, 24 Feb 2020 19:49:53 +0100
> Halil Pasic wrote:
>
> > On Mon, 24 Feb 2020 14:33:14 +1100
> > David Gibson wrote:
> >
> > > On Fri, Feb 21, 2020 at 07:07:02PM +0100, Halil Pasic wrote:
> > > > On Fri, 21 Feb 2020
On Mon, Feb 24, 2020 at 07:23:59PM +0100, Jean-Philippe Brucker wrote:
> The SMMUv3 driver, which can be built without CONFIG_PCI, will soon gain
> support for PRI. Partially revert commit c6e9aefbf9db ("PCI/ATS: Remove
> unused PRI and PASID stubs") to re-introduce the PRI stubs, and avoid
>
Subject could be simply "PCI/ATS: Export PRI functions"
On Mon, Feb 24, 2020 at 07:24:00PM +0100, Jean-Philippe Brucker wrote:
> The SMMUv3 driver uses pci_{enable,disable}_pri() and related
> functions. Export those functions to allow the driver to be built as a
> module.
>
> Cc: Bjorn Helgaas
On Thu, Feb 27, 2020 at 06:19:10PM +, Robin Murphy wrote:
> On 27/02/2020 1:48 pm, Russell King - ARM Linux admin wrote:
> > On Thu, Feb 27, 2020 at 01:44:56PM +, Robin Murphy wrote:
> > > On 27/02/2020 11:57 am, Russell King wrote:
> > > > On the LX2160A, there are lots (about 160) of
On Tue, Jan 28, 2020 at 03:00:14PM -0700, Jordan Crouse wrote:
> This is another iteration for the split pagetable support based on the
> suggestions from Robin and Will [1].
>
> Background: In order to support per-context pagetables the GPU needs to enable
> split tables so that we can store
On Mon, 24 Feb 2020 19:23:35 +0100
Jean-Philippe Brucker wrote:
> Shared Virtual Addressing (SVA) allows to share process page tables with
> devices using the IOMMU. Add a generic implementation of the IOMMU SVA
> API, and add support in the Arm SMMUv3 driver.
>
> Previous versions of this
Hi Baolu, Daniel,
Sorry for the delay. Was offline for the last week.
On Thu, 2020-02-20 at 19:58 +0800, Lu Baolu wrote:
> Hi,
>
> On 2020/2/20 18:06, Daniel Drake wrote:
> > > On Wed, Feb 19, 2020 at 11:40 AM Lu Baolu
> > > wrote:
> > > > With respect, this is problematical. The parent and
On 27/02/2020 1:48 pm, Russell King - ARM Linux admin wrote:
On Thu, Feb 27, 2020 at 01:44:56PM +, Robin Murphy wrote:
On 27/02/2020 11:57 am, Russell King wrote:
On the LX2160A, there are lots (about 160) of IOMMU messages produced
during boot; this is excessive. Reduce the severity of
On Mon, 24 Feb 2020 19:23:58 +0100
Jean-Philippe Brucker wrote:
> From: Jean-Philippe Brucker
>
> The SMMU provides a Stall model for handling page faults in platform
> devices. It is similar to PCI PRI, but doesn't require devices to have
> their own translation cache. Instead, faulting
On Mon, 24 Feb 2020 19:23:42 +0100
Jean-Philippe Brucker wrote:
> From: Jean-Philippe Brucker
>
> To enable address space sharing with the IOMMU, introduce mm_context_get()
> and mm_context_put(), that pin down a context and ensure that it will keep
> its ASID after a rollover. Export the
On Thu, Feb 27, 2020 at 01:44:56PM +, Robin Murphy wrote:
> On 27/02/2020 11:57 am, Russell King wrote:
> > On the LX2160A, there are lots (about 160) of IOMMU messages produced
> > during boot; this is excessive. Reduce the severity of these messages
> > to debug level.
>
> That's... a lot.
On 27/02/2020 11:57 am, Russell King wrote:
On the LX2160A, there are lots (about 160) of IOMMU messages produced
during boot; this is excessive. Reduce the severity of these messages
to debug level.
That's... a lot. Does the system really have that many devices, or is
some driver being
On the LX2160A, there are lots (about 160) of IOMMU messages produced
during boot; this is excessive. Reduce the severity of these messages
to debug level.
Signed-off-by: Russell King
---
drivers/iommu/iommu.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git
From: Diana Craciun
In ACPI the MC bus is represented as a platform device and a named
component in the IORT table. The mc-bus devices are discovered
dynamically at runtime but they share the same fwnode with the parent
platfom device. This patch changes the way the IRQ domain is searched
for
From: Makarand Pawagi
ACPI support is added in the fsl-mc driver. Driver will parse
MC DSDT table to extract memory and other resorces.
Interrupt (GIC ITS) information will be extracted from MADT table
by drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c.
IORT table will be parsed to configure DMA.
From: Laurentiu Tudor
Changing the way we configure dma for fsl-mc devices allows
us to get rid of our fsl-mc specific code in the generic
of iommu code.
Signed-off-by: Laurentiu Tudor
---
drivers/iommu/of_iommu.c | 20
1 file changed, 20 deletions(-)
diff --git
From: Laurentiu Tudor
The devices on this bus are not discovered by way of device tree
but by queries to the firmware. It makes little sense to trick the
generic of layer into thinking that these devices are of related so
that we can get our dma configuration. Instead of doing that, add
our
arch_rmrr_sanity_check() was introduced by commit f036c7fa0ab6 ("iommu/vt-d:
Check VT-d RMRR region in BIOS is reported as reserved") to detect RMRR
pointing to the area that might be used by OS as free memory. However the
check was based on E820_TYPE_RESERVED coverage and raised false alarms if
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