On Wed, Mar 11, 2020 at 01:44:57PM +0100, Jean-Philippe Brucker wrote:
> Each vendor has their own way of describing whether a host bridge
> supports ATS. The Intel and AMD ACPI tables selectively enable or
> disable ATS per device or sub-tree, while Arm has a single bit for each
> host bridge.
On Wed, Mar 11, 2020 at 01:45:00PM +0100, Jean-Philippe Brucker wrote:
> IOMMU drivers need to perform several tests when checking if a device
> supports ATS. Move them all into a new function that returns true when
> a device and its host bridge support ATS.
>
> Since pci_enable_ats() now calls
On Wed, Mar 11, 2020 at 01:44:59PM +0100, Jean-Philippe Brucker wrote:
> When initializing a PCI root bridge, copy its "ATS supported" attribute
> into the root bridge.
>
> Acked-by: Hanjun Guo
> Signed-off-by: Jean-Philippe Brucker
> ---
> drivers/acpi/arm64/iort.c | 27
On Wed, Mar 11, 2020 at 01:44:58PM +0100, Jean-Philippe Brucker wrote:
> When setting up a generic host on a device-tree based system, copy the
> ats-supported flag into the pci_host_bridge structure.
>
> Signed-off-by: Jean-Philippe Brucker
> ---
> v1->v2: keep the helper in pci-host-common.c
>
When we try to get an MSI cookie for a VFIO device, that can fail if
CONFIG_IOMMU_DMA is not set. In this case iommu_get_msi_cookie() returns
-ENODEV, and that should not be fatal.
Ignore that case and proceed with the initialisation.
This fixes VFIO with a platform device on the Calxeda Midway
pageno is an int and the PAGE_SHIFT shift is done on an int,
overflowing if the memory is bigger than 2G
This can be reproduced using for example a reserved-memory of 4G
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
On Thu, Mar 12, 2020 at 08:02:41PM +0800, Lu Baolu wrote:
> On 2020/3/12 19:37, Dan Carpenter wrote:
> > There were a couple places where we need to unlock before returning.
> >
> > Fixes: 91391b919e19 ("iommu/vt-d: Populate debugfs if IOMMUs are detected")
> > Signed-off-by: Dan Carpenter
> >
On 2020-03-12 6:28 am, Sai Prakash Ranjan wrote:
Hi Robin,
On 2020-03-10 22:14, Robin Murphy wrote:
On 10/03/2020 4:23 pm, Joerg Roedel wrote:
On Tue, Mar 10, 2020 at 07:30:50PM +0530, Sibi Sankar wrote:
The accesses are initiated by the firmware
and they access modem reserved regions.
On 2020/3/12 19:37, Dan Carpenter wrote:
There were a couple places where we need to unlock before returning.
Fixes: 91391b919e19 ("iommu/vt-d: Populate debugfs if IOMMUs are detected")
Signed-off-by: Dan Carpenter
---
drivers/iommu/intel-iommu-debugfs.c | 6 --
1 file changed, 4
Commit b9c6ff94e43a ("iommu/amd: Re-factor guest virtual APIC
(de-)activation code") accidentally left out the ir_data pointer when
calling modity_irte_ga(), which causes the function amd_iommu_update_ga()
to return prematurely due to struct amd_ir_data.ref is NULL and
the "is_run" bit of IRTE
On 2020/3/12 15:54, Jean-Philippe Brucker wrote:
Hi Baolu,
On Thu, Mar 12, 2020 at 09:44:16AM +0800, Lu Baolu wrote:
Hi Jean,
On 2020/3/11 20:45, Jean-Philippe Brucker wrote:
The pci_ats_supported() function checks if a device supports ATS and is
allowed to use it.
Signed-off-by:
Hi Baolu,
On Thu, Mar 12, 2020 at 09:44:16AM +0800, Lu Baolu wrote:
> Hi Jean,
>
> On 2020/3/11 20:45, Jean-Philippe Brucker wrote:
> > The pci_ats_supported() function checks if a device supports ATS and is
> > allowed to use it.
> >
> > Signed-off-by: Jean-Philippe Brucker
> > ---
> >
Hi Joerg,
There are another two small fixes queued in my tree.
Can you please consider them for v5.6?
Best regards,
-baolu
Daniel Drake (1):
iommu/vt-d: Ignore devices with out-of-spec domain number
Zhenzhong Duan (1):
iommu/vt-d: Fix the wrong printing in RHSA parsing
From: Zhenzhong Duan
When base address in RHSA structure doesn't match base address in
each DRHD structure, the base address in last DRHD is printed out.
This doesn't make sense when there are multiple DRHD units, fix it
by printing the buggy RHSA's base address.
Signed-off-by: Zhenzhong Duan
From: Daniel Drake
VMD subdevices are created with a PCI domain ID of 0x1 or
higher.
These subdevices are also handled like all other PCI devices by
dmar_pci_bus_notifier().
However, when dmar_alloc_pci_notify_info() take records of such devices,
it will truncate the domain ID to a u16
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