[PATCH] iommu: amd: Fix IO_PAGE_FAULT due to __unmap_single() size overflow

Currently, an integer is used to specify the size in unmap_sg(). With 2GB worth of pages (512k 4k pages), it requires 31 bits (i.e. (1 << 19) << 12), which overflows the integer, and ends up unmapping more pages than intended. Subsequently, this results in IO_PAGE_FAULT. Uses size_t instead of int

DMAR errors on Wildcat Point-LP xHCI (Lenovo T450s)

Hello, Trying to use a built-in USB device I rarely use (Sierra EM7345 LTE modem), I ran into issues from the modem flapping (getting removed from USB bus before LTE network registration is visible) up to all devices on the bus being "disconnected" (xhci giving up, in my understanding, with only t

Re: [PATCH] iommu/amd: Fix event counter availability check

Dear Alexander, Thank you very much for the patch. Am 31.05.20 um 09:22 schrieb Alexander Monakov: Adding Shuah Khan to Cc: I've noticed you've seen this issue on Ryzen 2400GE; can you have a look at the patch? Would be nice to know if it fixes the problem for you too. On Fri, 29 May 2020

[PATCH 1/2] iommu/vt-d: Make Intel SVM code 64-bit only

Current Intel SVM is designed by setting the pgd_t of the processor page table to FLPTR field of the PASID entry. The first level translation only supports 4 and 5 level paging structures, hence it's infeasible for the IOMMU to share a processor's page table when it's running in 32-bit mode. Let's

[PATCH 0/2] iommu/vt-d: Two fixes for v5.8

Hi Joerg, This encloses two fixes for v5.8. - Make Intel SVM code 64-bit only - Set U/S bit to make IOVA over first level compatible with 2nd level translations. Best regards, baolu Lu Baolu (2): iommu/vt-d: Make Intel SVM code 64-bit only iommu/vt-d: Set U/S bit in first level page table

[PATCH 2/2] iommu/vt-d: Set U/S bit in first level page table by default

When using first-level translation for IOVA, currently the U/S bit in the page table is cleared which implies DMA requests with user privilege are blocked. As the result, following error messages might be observed when passing through a device to user level: DMAR: DRHD: handling fault status reg 3

Re: [PATCH] iommu/amd: Fix event counter availability check

Hi, Adding Shuah Khan to Cc: I've noticed you've seen this issue on Ryzen 2400GE; can you have a look at the patch? Would be nice to know if it fixes the problem for you too. Thanks. Alexander On Fri, 29 May 2020, Alexander Monakov wrote: > The driver performs an extra check if the IOMMU's capa