On Tue, 2020-07-21 at 11:10 +0200, David Hildenbrand wrote:
> On 21.07.20 04:16, Miles Chen wrote:
> > In previous discussion [1] and [2], we found that it is risky to
> > use max_pfn or totalram_pages to tell if 4GB mode is enabled.
> >
> > Check 4GB mode by reading infracfg register, remove the
On Tue, 2020-07-21 at 23:19 +0200, Matthias Brugger wrote:
>
> On 21/07/2020 13:24, Yong Wu wrote:
> > On Tue, 2020-07-21 at 11:40 +0200, Matthias Brugger wrote:
> >>
> >> On 21/07/2020 04:16, Miles Chen wrote:
> >>> In previous discussion [1] and [2], we found that it is risky to
> >>> use max_pf
On 7/22/20 10:40 AM, Lu Baolu wrote:
Hi Jun,
On 7/22/20 10:26 AM, Miao, Jun wrote:
Kernel panic - not syncing: DMAR hardware is malfunctioning
CPU: 0 PID: 347 Comm: rtcwake Not tainted 5.4.0-yocto-standard #124
Hardware name: Intel Corporation Ice Lake Client Platform/IceLake U
DDR4
SODIMM PD
On 7/22/20 11:07 AM, Lu Baolu wrote:
On 7/22/20 11:03 AM, Jun Miao wrote:
On 7/22/20 10:40 AM, Lu Baolu wrote:
Hi Jun,
On 7/22/20 10:26 AM, Miao, Jun wrote:
Kernel panic - not syncing: DMAR hardware is malfunctioning
CPU: 0 PID: 347 Comm: rtcwake Not tainted 5.4.0-yocto-standard #124
Hardware
On Wed, 2020-07-22 at 15:17 +0800, Miles Chen wrote:
> On Tue, 2020-07-21 at 23:19 +0200, Matthias Brugger wrote:
> >
> > On 21/07/2020 13:24, Yong Wu wrote:
> > > On Tue, 2020-07-21 at 11:40 +0200, Matthias Brugger wrote:
> > >>
> > >> On 21/07/2020 04:16, Miles Chen wrote:
> > >>> In previous di
Hi Lu, limonciello.
Yestoday i just verified the issue with the patch. and just iommu Subscription
today.This is my test log.
[Hardware info]
Intel(R) Core(TM) i7-1065G7 CPU @ 1.30GHz 1.20GHz
ICLSFWR1.R00.3162.A00.1904162000
BIOS Information
BIOS Vendo Intel
Core Version
Hi
[This is an automated email]
This commit has been processed because it contains a "Fixes:" tag
fixing commit: .
The bot has tested the following trees: v5.7.9, v5.4.52, v4.19.133, v4.14.188,
v4.9.230, v4.4.230.
v5.7.9: Failed to apply! Possible dependencies:
Unable to calculate
v5.4.52
On Fri, Jul 17, 2020 at 03:15:43PM +, Sironi, Filippo wrote:
> I don't believe that we want to trust a userspace driver here, this may
> result in hosts becoming unstable because devices are asked to do things
> they aren't meant to do (e.g., DMA beyond 48 bits).
How is the hosts stability aff
On Wed, 2020-07-22 at 14:19 +0200, j...@8bytes.org wrote:
>
> On Fri, Jul 17, 2020 at 03:15:43PM +, Sironi, Filippo wrote:
> > I don't believe that we want to trust a userspace driver here, this
> > may
> > result in hosts becoming unstable because devices are asked to do
> > things
> > they a
On Tue, Jul 14, 2020 at 12:42:36PM +0100, Robin Murphy wrote:
> Oh bother - yes, this could have been masking all manner of bugs. That
> system will presumably also break if you managed to exhaust the 32-bit IOVA
> space such that the allocator moved up to the higher range anyway, or if you
> passe
On Tue, Jul 14, 2020 at 11:20:53AM +0100, Lad Prabhakar wrote:
> Lad Prabhakar (1):
> iommu/ipmmu-vmsa: Add an entry for r8a77961 in soc_rcar_gen3[]
>
> Marian-Cristian Rotariu (1):
> iommu/ipmmu-vmsa: Hook up R8A774E1 DT matching code
Applied, thanks.
On Tue, Jul 14, 2020 at 12:59:28PM +0100, Robin Murphy wrote:
> The name "update_pte" is a little too generic, and can end up clashing
> with architecture pagetable code leaked out of common mm headers. Rename
> it to something more appropriately namespaced.
>
> Reported-by: kernel test robot
> A
On Tue, Jul 14, 2020 at 08:22:11PM +0100, Colin King wrote:
> From: Colin Ian King
>
> It is possible for the call to omap_iommu_dump_ctx to return
> a negative error number, so check for the failure and return
> the error number rather than pass the negative value to
> simple_read_from_buffer.
>
On Tue, Jul 21, 2020 at 12:45:17AM +0530, Naresh Kamboju wrote:
> On Mon, 20 Jul 2020 at 21:21, Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > The device may be torn down, but the domain should still be valid. Lets
> > use that as the tlb flush ops cookie.
> >
> > Fixes a problem reported in [
Hi Will,
On Tue, Jul 21, 2020 at 09:03:53AM +0100, Will Deacon wrote:
> Please pull these Arm SMMU driver updates for 5.9. Summary is in the tag,
> but the main thing is support for two new SoC integrations, one of which
> is considerably more brain-dead than the other (determining which one is
>
On Tue, Jul 14, 2020 at 06:23:54PM +, Prakhya, Sai Praneeth wrote:
> Q1:
> > Presently, iommu_change_dev_def_domain() checks if the iommu group still has
> > only one device or not. Hence, checking if iommu group has one device or
> > not is
> > done twice, once before taking device_lock() and
On Wed, Jul 22, 2020 at 12:34:57PM +, Sironi, Filippo wrote:
> On Wed, 2020-07-22 at 14:19 +0200, j...@8bytes.org wrote:
> I wouldn't be surprised if a PCIe device raises a PCIe SERR if it is
> asked to do DMA beyond its abilities.
Yeah, but that would also make it impossible to safely assign
On Mon, Jul 13, 2020 at 04:47:56PM -0700, Fenghua Yu wrote:
> PASID is defined as a few different types in iommu including "int",
> "u32", and "unsigned int". To be consistent and to match with uapi
> definitions, define PASID and its variations (e.g. max PASID) as "u32".
> "u32" is also shorter an
On Mon, Jul 13, 2020 at 10:25:42PM +0800, Wei Yongjun wrote:
> The sparse tool complains as follows:
>
> drivers/iommu/iommu.c:386:5: warning:
> symbol 'iommu_insert_resv_region' was not declared. Should it be static?
> drivers/iommu/iommu.c:2182:5: warning:
> symbol '__iommu_map' was not declar
On Sun, Jun 28, 2020 at 11:12:50PM +1200, Barry Song wrote:
> This is useful for at least two scenarios:
> 1. ARM64 smmu will get memory from local numa node, it can save its
> command queues and page tables locally. Tests show it can decrease
> dma_unmap latency at lot. For example, without this p
In previous discussion [1] and [2], we found that it is risky to
use max_pfn or totalram_pages to tell if 4GB mode is enabled.
Check 4GB mode by reading infracfg register, remove the usage
of the un-exported symbol max_pfn.
This is a step towards building mtk_iommu as a kernel module.
---
Chang
On Sun, Jun 28, 2020 at 11:12:50PM +1200, Barry Song wrote:
> struct page *dma_alloc_contiguous(struct device *dev, size_t size, gfp_t gfp)
> {
> size_t count = size >> PAGE_SHIFT;
> struct page *page = NULL;
> struct cma *cma = NULL;
> + int nid = dev ? dev_to_node(dev) : N
Split out a cma_alloc_aligned helper to deal with the "interesting"
calling conventions for cma_alloc, which then allows to the main
function to be written straight forward. This also takes advantage
of the fact that NULL dev arguments have been gone from the DMA API
for a while.
Signed-off-by: C
On Wed, Jul 22, 2020 at 6:10 AM Joerg Roedel wrote:
>
> On Tue, Jul 21, 2020 at 12:45:17AM +0530, Naresh Kamboju wrote:
> > On Mon, 20 Jul 2020 at 21:21, Rob Clark wrote:
> > >
> > > From: Rob Clark
> > >
> > > The device may be torn down, but the domain should still be valid. Lets
> > > use th
On 22/07/2020 16:19, Miles Chen wrote:
In previous discussion [1] and [2], we found that it is risky to
use max_pfn or totalram_pages to tell if 4GB mode is enabled.
Check 4GB mode by reading infracfg register, remove the usage
of the un-exported symbol max_pfn.
This is a step towards buildi
On Wed, Jul 22, 2020 at 07:54:40AM -0700, Rob Clark wrote:
> On Wed, Jul 22, 2020 at 6:10 AM Joerg Roedel wrote:
> > Is this needed for v5.8/stable? A fixes tag would be great too.
>
> looks like, yes:
>
> Fixes: 09b5dfff9ad6 ("iommu/qcom: Use accessor functions for iommu
> private data")
Thank
Hi Joerg,
Thanks for the reply. I will spin another version of the patch addressing your
comments.
> -Original Message-
> From: Joerg Roedel
> Sent: Wednesday, July 22, 2020 6:53 AM
> To: Prakhya, Sai Praneeth
> Cc: Raj, Ashok ; Will Deacon ;
> iommu@lists.linux-foundation.org; Robin M
Hi, Joerg,
On Wed, Jul 22, 2020 at 04:03:40PM +0200, Joerg Roedel wrote:
> On Mon, Jul 13, 2020 at 04:47:56PM -0700, Fenghua Yu wrote:
> > PASID is defined as a few different types in iommu including "int",
> > "u32", and "unsigned int". To be consistent and to match with uapi
> > definitions, def
On Wed, 22 Jul 2020 09:01:27 +0800
Lu Baolu wrote:
> >
> > Not sure what state is this patch in, there is a bug in this patch
> > (see below), shall I send out an updated version of this one only?
> > or another incremental patch.
>
> Please send an updated version. I hope Joerg could pick th
Hi Baolu and all,
This is a series to address some of the issues we found in vSVA support.
Most of the patches deal with exception handling, we also removed some bits
that are not currently supported.
Many thanks to Kevin Tian's review.
Jacob & Yi
Changelog:
v5 Fix off by one bug in 4/7
From: Liu Yi L
Set proper masks to avoid invalid input spillover to reserved bits.
Acked-by: Lu Baolu
Reviewed-by: Eric Auger
Signed-off-by: Liu Yi L
Signed-off-by: Jacob Pan
---
include/linux/intel-iommu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/linu
DevTLB flush can be used for both DMA request with and without PASIDs.
The former uses PASID#0 (RID2PASID), latter uses non-zero PASID for SVA
usage.
This patch adds a check for PASID value such that devTLB flush with
PASID is used for SVA case. This is more efficient in that multiple
PASIDs can b
Global pages support is removed from VT-d spec 3.0 for dev TLB
invalidation. This patch is to remove the bits for vSVA. Similar change
already made for the native SVA. See the link below.
Link: https://lkml.org/lkml/2019/8/26/651
Acked-by: Lu Baolu
Reviewed-by: Eric Auger
Signed-off-by: Jacob Pa
For guest requested IOTLB invalidation, address and mask are provided as
part of the invalidation data. VT-d HW silently ignores any address bits
below the mask. SW shall also allow such case but give warning if
address does not align with the mask. This patch relax the fault
handling from error to
From: Liu Yi L
For guest SVA usage, in order to optimize for less VMEXIT, guest request
of IOTLB flush also includes device TLB.
On the host side, IOMMU driver performs IOTLB and implicit devTLB
invalidation. When PASID-selective granularity is requested by the guest
we need to derive the equiva
From: Liu Yi L
Address information for device TLB invalidation comes from userspace
when device is directly assigned to a guest with vIOMMU support.
VT-d requires page aligned address. This patch checks and enforce
address to be page aligned, otherwise reserved bits can be set in the
invalidation
For the unlikely use case where multiple aux domains from the same pdev
are attached to a single guest and then bound to a single process
(thus same PASID) within that guest, we cannot easily support this case
by refcounting the number of users. As there is only one SL page table
per PASID while we
>Is the problem on SDM630 that when you write to SMR/S2CR the device
>reboots? Or that when you start writing out the context bank
>configuration that trips the display and the device reboots?
I added some debug prints and the phone hangs after reaching the
seventh CB (with i=6) at
arm_smmu_cb_wr
> -Original Message-
> From: Christoph Hellwig [mailto:h...@lst.de]
> Sent: Thursday, July 23, 2020 2:17 AM
> To: Song Bao Hua (Barry Song)
> Cc: h...@lst.de; m.szyprow...@samsung.com; robin.mur...@arm.com;
> w...@kernel.org; ganapatrao.kulka...@cavium.com;
> catalin.mari...@arm.com; io
> -Original Message-
> From: Christoph Hellwig [mailto:h...@lst.de]
> Sent: Thursday, July 23, 2020 2:30 AM
> To: Song Bao Hua (Barry Song)
> Cc: h...@lst.de; m.szyprow...@samsung.com; robin.mur...@arm.com;
> w...@kernel.org; ganapatrao.kulka...@cavium.com;
> catalin.mari...@arm.com; io
On Tue, Jul 21, 2020 at 8:51 AM Christoph Hellwig wrote:
>
> On Wed, Jul 15, 2020 at 10:35:11AM -0400, Jim Quinlan wrote:
> > The new field 'dma_range_map' in struct device is used to facilitate the
> > use of single or multiple offsets between mapping regions of cpu addrs and
> > dma addrs. It s
On 7/23/20 3:26 AM, Jacob Pan wrote:
DevTLB flush can be used for both DMA request with and without PASIDs.
The former uses PASID#0 (RID2PASID), latter uses non-zero PASID for SVA
usage.
This patch adds a check for PASID value such that devTLB flush with
PASID is used for SVA case. This is more
The VT-d spec requires (10.4.4 Global Command Register, TE field) that:
Hardware implementations supporting DMA draining must drain any in-flight
DMA read/write requests queued within the Root-Complex before completing
the translation enable command and reflecting the status of the command
through
On 7/22/20 7:45 AM, Limonciello, Mario wrote:
-Original Message-
From: Lu Baolu
Sent: Tuesday, July 21, 2020 6:07 PM
To: Limonciello, Mario; Joerg Roedel
Cc: baolu...@linux.intel.com; Ashok Raj; linux-ker...@vger.kernel.org;
sta...@vger.kernel.org; Koba Ko; iommu@lists.linux-foundatio
On Wed, 2020-07-22 at 17:19 +0200, Matthias Brugger wrote:
>
> On 22/07/2020 16:19, Miles Chen wrote:
> > In previous discussion [1] and [2], we found that it is risky to
> > use max_pfn or totalram_pages to tell if 4GB mode is enabled.
> >
> > Check 4GB mode by reading infracfg register, remove
In previous discussion [1] and [2], we found that it is risky to
use max_pfn or totalram_pages to tell if 4GB mode is enabled.
Check 4GB mode by reading infracfg register, remove the usage
of the un-exported symbol max_pfn.
This is a step towards building mtk_iommu as a kernel module.
[1] https:
Hi Nicolas,
Sorry I got stuck on other things yesterday.
On Tue, 21 Jul 2020 at 21:57, Nicolas Saenz Julienne
wrote:
>
> On Tue, 2020-07-21 at 20:52 +0530, Amit Pundir wrote:
>
> [...]
>
> > > > > Can you try booting *without* my patch and this in the kernel
> > > > > command
> > > > > line: "cm
On Wed, Jul 22, 2020 at 04:43:07PM +0200, Christoph Hellwig wrote:
> Split out a cma_alloc_aligned helper to deal with the "interesting"
> calling conventions for cma_alloc, which then allows to the main
> function to be written straight forward. This also takes advantage
> of the fact that NULL d
On Wed, Jul 22, 2020 at 11:00:48PM -0700, Nicolin Chen wrote:
> On Wed, Jul 22, 2020 at 04:43:07PM +0200, Christoph Hellwig wrote:
> > Split out a cma_alloc_aligned helper to deal with the "interesting"
> > calling conventions for cma_alloc, which then allows to the main
> > function to be written
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